Pattern verification method, program thereof, and manufacturing method of semiconductor device

Abstract

A verification method of an integrated circuit pattern includes extracting a pattern which is not greater than a preset pattern size, extracting a pattern edge as a target of lithography simulation from the extracted pattern, and performing the lithography simulation on the extracted pattern edge to verify the integrated circuit pattern.

1 . An integrated circuit pattern verification method comprising: 
 extracting a pattern which is not greater than a preset pattern size;    extracting a pattern edge as a target of lithography simulation from the extracted pattern; and    performing the lithography simulation on the extracted pattern edge to verify the pattern.    
   
   
       2 . The integrated circuit pattern verification method according to  claim 1 , wherein said extracting a pattern which is not greater than a preset pattern size includes extracting a pattern which is not greater than a preset size from pattern data subjected to optical proximity correction.  
   
   
       3 . The integrated circuit pattern verification method according to  claim 1 , wherein said performing the lithography simulation to verify the pattern includes comparing a pattern obtained by performing the lithography simulation with a design pattern to extract a pattern edge portion including a deviation which is not smaller than a preset value.  
   
   
       4 . An integrated circuit pattern verification method comprising: 
 sorting integrated circuit patterns into a plurality of pattern groups based on pattern sizes or pattern types; and    performing lithography simulation on the plurality of sorted pattern groups while changing respective conditions to verify the patterns.    
   
   
       5 . The integrated circuit pattern verification method according to  claim 4 , wherein said performing the lithography includes performing size check based on design rules with respect to a pattern to which a tolerance which is not smaller than a specified value is allowed, a pattern whose minimum size alone is specified and a pattern whose environment is substantially fixed within a specified objective range.  
   
   
       6 . The integrated circuit pattern verification method according to  claim 4 , wherein said sorting into a plurality of pattern groups based on pattern sizes or pattern types includes performing sorting based on at least one selected from the group consisting of pattern sizes, levels of device importance and pattern densities.  
   
   
       7 . The integrated circuit pattern verification method according to  claim 4 , wherein said performing the lithography simulation while changing respective conditions to verify the patterns includes performing the lithography simulation while changing at least one condition selected from the group consisting of the number of evaluation points with which the simulation is carried out, a model of the simulation, an objective range taken into the simulation and an error cause taken into the simulation.  
   
   
       8 . A computer program for integrated circuit pattern verification, the program being stored in a computer-readable medium, the program comprising: 
 extracting a pattern which is not greater than a preset pattern size;    extracting a pattern edge as a target of lithography simulation from the extracted pattern; and    performing simulation with respect to the extracted pattern edge to verify the pattern.    
   
   
       9 . The computer program for integrated circuit pattern verification according to  claim 8 , wherein said extracting a pattern which is not greater than a preset pattern size includes extracting a pattern which is not greater than a preset size from pattern data subjected to optical proximity correction.  
   
   
       10 . The computer program for integrated circuit pattern verification according to  claim 8 , wherein said performing lithography simulation to verify the pattern includes comparing a pattern obtained by effecting the lithography simulation with a design pattern to extract a pattern edge portion including a deviation which is not smaller than a specified value.  
   
   
       11 . A computer program for integrated circuit pattern verification, the program being stored in a computer-readable storage, the program comprising: 
 sorting integrated circuit patterns into a plurality of pattern groups based on pattern sizes or pattern types; and    performing lithography simulation on the plurality of sorted pattern groups while changing respective conditions to verify the patterns.    
   
   
       12 . The computer program for integrated circuit pattern verification according to  claim 4 , wherein said performing lithography simulation on a pattern to which a tolerance which is not smaller than a specified value is allowed, a pattern whose minimum size alone is specified and a pattern whose environment is substantially fixed within a specified objective range includes performing size check based on design rules.  
   
   
       13 . The program for integrated circuit pattern verification according to  claim 11 , wherein said sorting into a plurality of pattern groups based on pattern sizes or pattern types includes sorting based on at least one selected from the group consisting of pattern sizes, levels of device importance and pattern densities.  
   
   
       14 . The computer program for integrated circuit pattern verification according to  claim 11 , wherein said performing lithography simulation while changing respective conditions to verify the patterns includes performing the lithography simulation while changing at least one condition selected from the group consisting of the number of evaluation points with which the simulation is effected, a model of the simulation, an objective range which is taken into the simulation and an error cause which is taken into the simulation.  
   
   
       15 . A manufacturing method of a semiconductor device, comprising: 
 preparing design pattern data;    processing the design pattern data for creation of a mask, the processing including extracting a pattern which is not greater than a preset pattern size,    extracting a pattern edge as a target of lithography simulation from the extracted pattern, and    performing simulation on the extracted pattern edge to verify the pattern;    creating a mask from the processed design pattern data;    forming a predetermined film on a semiconductor wafer and then patterning the predetermined film by photolithography using the predetermined film to form wiring lines;    dicing the semiconductor wafer to form a plurality of chips; and    mounting each of the plurality of chips on a predetermined package and connecting the wiring lines to package terminals to perform electrical inspection.    
   
   
       16 . The manufacturing method of a semiconductor device according to  claim 15 , wherein said extracting a pattern which is not greater than a preset pattern size includes extracting a pattern which is not greater than a preset size from pattern data subjected to optical proximity correction.  
   
   
       17 . The manufacturing method of a semiconductor device according to  claim 15 , wherein said performing the lithography simulation to verify the pattern includes comparing a pattern obtained by performing the lithography simulation with a design pattern to extract the pattern edge portion including a deviation which is not smaller than a specified value.  
   
   
       18 . A manufacturing method of a semiconductor device, comprising: 
 preparing design pattern data;    processing the design pattern data for creation of a mask, the processing including    sorting integrated circuit patterns into a plurality of pattern groups based on pattern sizes or pattern types, and    performing lithography simulation to the plurality of sorted pattern groups while changing respective conditions to verify the patterns;    creating a mask from the new design pattern;    forming a predetermined film on a semiconductor wafer and then patterning the predetermined film by photolithography using the mask to form wiring lines;    dicing the semiconductor wafer to form a plurality of chips; and    mounting each of the plurality of chips on a predetermined package and connecting the wiring lines to package terminals to perform electrical inspection.    
   
   
       19 . The manufacturing method of a semiconductor device according to  claim 18 , wherein said performing the lithography simulation with respect to a pattern to which a tolerance which is not smaller than a specified value is allowed, a pattern whose minimum size alone is specified and a pattern whose environment is substantially fixed within a specified objective range includes effecting size check based on design rules.  
   
   
       20 . The manufacturing method of a semiconductor device according to  claim 18 , wherein said sorting into a plurality of pattern groups based on pattern sizes or pattern types includes sorting based on at least one selected from the group consisting of pattern sizes, levels of device importance and pattern densities.