Method, system, and apparatus for adjacent-symbol error correction and detection code

Abstract

A circuit and method for generating an Error Correcting Code (ECC) based on an adjacent symbol codeword that is formed in two clock phases.

1 . A method for testing a memory comprising: 
 generating a plurality of check bits to append to data that is forwarded to the memory;    generating an adjacent symbol codeword based at least in part on data received from the memory;    decoding the adjacent symbol codeword; and    determining whether an error exists in the memory.    
   
   
       2 . The method of  claim 1  wherein decoding the adjacent symbol codeword comprises generating a syndrome based at least in part on the adjacent symbol codeword.  
   
   
       3 . The method of  claim 1  wherein determining whether an error exists in the memory is based at least in part on the syndrome.  
   
   
       4 . The method of  claim 3  wherein an error exists based on the syndrome, further comprising: 
 classifying the error in the received data; and    correcting the error in the received data.    
   
   
       5 . The method of  claim 1  wherein the memory is a Double Data Rate (DDR) memory.  
   
   
       6 . The method of  claim 2  wherein the syndrome is thirty two bits based on a two hundred eighty eight bit codeword.