Hardware support for superpage coalescing

Abstract

A method of assigning virtual memory to physical memory in a data processing system allocates a set of contiguous physical memory pages for a new page mapping, instructs the memory controller to move the virtual memory pages according to the new page mapping, and then allows access to the virtual memory pages using the new page mapping while the memory controller is still copying the virtual memory pages to the set of physical memory pages. The memory controller can use a mapping table which temporarily stores entries of the old and new page addresses, and releases the entries as copying for each entry is completed. The translation look aside buffer (TLB) entries in the processor cores are updated for the new page addresses prior to completion of copying of the memory pages by the memory controller. The invention can be extended to non-uniform memory array (NUMA) systems. For systems with cache memory, any cache entry which is affected by the page move can be updated by modifying its address tag according to the new page mapping. This tag modification may be limited to cache entries in a dirty coherency state. The cache can further relocate a cache entry based on a changed congruence class for any modified address tag.

1 - 20 . (canceled)  
   
   
       21 . A cache memory for a processing unit, comprising: 
 a data array which stores values associated with respective locations in system memory;    a tag array which stores address tags corresponding to the values in said data array;    a cache controller which receives cache instructions and accesses said data array and said tag array to carry out read and write operations; and    a state machine which modifies an address tag for a cache entry based on a new memory mapping for an associated memory location of the cache entry.    
   
   
       22 . The cache memory of  claim 21  wherein said state machine modifies the address tag in response to a determination that the cache entry has a dirty coherency state.  
   
   
       23 . The cache memory of  claim 21  wherein said cache controller relocates the cache entry based on a changed congruence class for the modified address tag.  
   
   
       24 . The cache memory of  claim 23  wherein said cache controller makes a determination that there is no available cache line in the changed congruence class for the modified address tag, and evicts another cache entry in the changed congruence class to make that entry available.  
   
   
       25 . The cache memory of  claim 21  wherein said state machine modifies the address tag in response to a determination that the cache entry has a clean coherency state.  
   
   
       26 . The cache memory of  claim 21  wherein said state machine examines each of the address tags in said tag array to determine that the address tag for the cache entry is affected by the new memory mapping.  
   
   
       27 . A method of updating a cache memory of a computer system, comprising: 
 receiving migration instructions having a new memory mapping;    examining address tags in a tag array of the cache memory to determine that at least one address tag having an associated cache entry is affected by the new memory mapping; and    modifying the address tag for the cache entry based on the new memory mapping.    
   
   
       28 . The cache memory of  claim 27  wherein the address tag for the cache entry is modified in response to a determination that the cache entry has a dirty coherency state.  
   
   
       29 . The cache memory of  claim 27  wherein the address tag for the cache entry is modified in response to a determination that the cache entry has a clean coherency state.  
   
   
       30 . The cache memory of  claim 27  further comprising relocating the cache entry based on a changed congruence class for the modified address tag.  
   
   
       31 . The cache memory of  claim 30  further comprising: 
 determining that there is no available cache line in the changed congruence class for the modified address tag; and    evicting another cache entry in the changed congruence class to make that entry available.    
   
   
       32 . A computer system comprising: 
 a processing unit;    a memory array storing program instructions which are processed by said processing unit; and    a cache memory having 
 a data array which stores values associated with respective locations in said memory array,  
 a tag array which stores address tags corresponding to the values in said data array,  
 a cache controller which receives cache instructions and accesses said data array and said tag array to carry out read and write operations, and  
 a state machine which modifies an address tag for a cache entry based on a new memory mapping for an associated memory location of the cache entry.  
   
   
   
       33 . The computer system of  claim 32  wherein said state machine modifies the address tag in response to a determination that the cache entry has a dirty coherency state.  
   
   
       34 . The computer system of  claim 32  wherein said state machine modifies the address tag in response to a determination that the cache entry has a clean coherency state.  
   
   
       35 . The computer system of  claim 32  wherein said state machine examines each of the address tags in said tag array to determine that the address tag for the cache entry is affected by the new memory mapping.  
   
   
       36 . The computer system of  claim 32  wherein: 
 said cache memory is one of a plurality of cache memories in the computer system; and    the program instructions include an operating system which broadcasts migration instructions having the new memory mapping to all of said cache memories.    
   
   
       37 . The computer system of  claim 32  wherein said cache controller relocates the cache entry based on a changed congruence class for the modified address tag.  
   
   
       38 . The computer system of  claim 37  wherein said cache controller makes a determination that there is no available cache line in the changed congruence class for the modified address tag, and evicts another cache entry in the changed congruence class to make that entry available.