Clock distribution networks and conductive lines in semiconductor integrated circuits

Abstract

A clock distribution network ( 110 ) is formed on a semiconductor interposer ( 320 ) which is a semiconductor integrated circuit. An input terminal ( 120 ) of the clock distribution network is formed on one side of the interposer, and output terminals ( 130 ) of the clock distribution network are formed on the opposite side of the interposer. The interposer has a through hole ( 360 ), and the clock distribution network includes a conductive feature going through the through hole. The side of the interposer which has the output terminals ( 130 ) is bonded to a second integrated circuit ( 310 ) containing circuitry clocked by the clock distribution network. The other side of the interposer is bonded to a third integrated circuit or a wiring substrate ( 330 ). The interposer contains a ground structure, or ground structures ( 390, 510 ), that shield circuitry from the clock distribution network. Conductive lines ( 150 ) in an integrated circuit are formed in trenches ( 610 ) in a semiconductor substrate.

1 . A method for operating an integrated circuit, the integrated circuit comprising: 
 a trench in a semiconductor substrate;    a conductive line in the trench to interconnect two laterally spaced nodes of circuitry;    a first conductive layer located between the conductive line and surfaces of the trench;    a first dielectric insulating the first conductive layer from the conductive line; and    a second dielectric between the first conductive layer and surfaces of the trench;    the method comprising holding the first conductive layer at a constant voltage while providing an alternating voltage on the conductive line when the integrated circuit is operated.    
   
   
       2 . The method of  claim 1  wherein the two nodes are located at two different ends of the conductive line.  
   
   
       3 . The method of  claim 1  wherein the trench is part of a trench network having conductive lines formed therein.  
   
   
       4 . The method of  claim 1  wherein the integrated circuit further comprises dielectric insulating the conductive line from the substrate.  
   
   
       5 . The method of  claim 1  wherein the first conductive layer is formed before the conductive line.  
   
   
       6 . The method of  claim 1  wherein the first conductive layer is present below a top surface of the conductive line.  
   
   
       7 . The method of  claim 1  wherein the first conductive layer is present below the conductive line above the trench's bottom surface.  
   
   
       8 . The method of  claim 1  wherein the conductive line is part of a clock distribution network.  
   
   
       9 . The method of  claim 1  wherein the integrated circuit further comprises a third dielectric overlying the conductive line, and a second conductive layer overlying the conductive line and insulated from the conductive line by the third dielectric, with at least a portion of the second conductive layer lying directly above at least a portion of the conductive line, wherein the second conductive layer physically contacts the first conductive layer so as to be at the same voltage as the first conductive layer.  
   
   
       10 . The method of  claim 9  wherein the second conductive layer crosses over the trench over the conductive line.  
   
   
       11 . A manufacturing method comprising: 
 forming a trench in a semiconductor substrate; and    forming a conductive line in the trench to interconnect two laterally spaced nodes of circuitry;    forming a first conductive layer located between the conductive line and surfaces of the trench;    forming a first dielectric insulating the first conductive layer from the conductive line; and    before forming the first conductive layer, forming a second dielectric between the first conductive layer and surfaces of the trench;    wherein the trench is part of a tree network of trenches, and the conductive line is part of a tree network of conductive lines.    
   
   
       12 . The method of  claim 11  wherein the first conductive layer is formed before the conductive line.  
   
   
       13 . The method of  claim 11  wherein the first conductive layer is present below a top surface of the conductive line.  
   
   
       14 . The method of  claim 11  wherein the first conductive layer is present below the conductive line above the trench's bottom surface.  
   
   
       15 . A manufacturing method comprising: 
 forming a trench in a semiconductor substrate; and    forming a conductive line in the trench to interconnect two laterally spaced nodes of circuitry;    forming a first conductive layer located between the conductive line and surfaces of the trench;    forming a first dielectric insulating the first conductive layer from the conductive line; and    before forming the first conductive layer, forming a second dielectric between the first conductive layer and surfaces of the trench;    wherein the trench is part of a trench network comprising a grid of trenches, and the conductive line is part of a grid network of conductive lines.    
   
   
       16 . The method of  claim 15  wherein the first conductive layer is formed before the conductive line.  
   
   
       17 . The method of  claim 15  wherein the first conductive layer is present below a top surface of the conductive line.  
   
   
       18 . The method of  claim 15  wherein the first conductive layer is present below the conductive line above the trench's bottom surface.  
   
   
       19 . A method for operating an integrated circuit, the integrated circuit comprising: 
 a trench in a semiconductor substrate;    a conductive line in the trench;    a first conductive layer located between the conductive line and surfaces of the trench;    a first dielectric insulating the first conductive layer from the conductive line; and    a second dielectric between the first conductive layer and surfaces of the trench;    the method comprising holding the first conductive layer at a constant voltage while providing a clock signal on the conductive line when the integrated circuit is operated.    
   
   
       20 . The method of  claim 19  wherein the trench is part of a trench network having conductive lines formed therein which comprise said conductive line on which the clock signal is provided.  
   
   
       21 . The method of  claim 19  wherein the integrated circuit further comprises dielectric insulating the conductive line from the substrate.  
   
   
       22 . The method of  claim 19  wherein the first conductive layer is present below a top surface of the conductive line.  
   
   
       23 . The method of  claim 19  wherein the first conductive layer is present below the conductive line above the trench's bottom surface.  
   
   
       24 . The method of  claim 19  wherein the integrated circuit further comprises a third dielectric overlying the conductive line, and a second conductive layer overlying the conductive line and insulated from the conductive line by the third dielectric, wherein the second conductive layer crosses over the trench over the conductive line, wherein the second conductive layer physically contacts the first conductive layer so as to be at the same voltage as the first conductive layer.