Structures with planar strained layers

Abstract

A structure and a method for forming the structure, the method including forming a compressively strained semiconductor layer, the compressively strained layer having a strain greater than or equal to 0.25%. A tensilely strained semiconductor layer is formed over the compressively strained layer. The compressively strained layer is substantially planar, having a surface roughness characterized in (i) having an average wavelength greater than an average wavelength of a carrier in the compressively strained layer or (ii) having an average height less than 10 nm.

1 .- 47 . (canceled)  
   
   
       48 . A method for forming a structure, the method comprising: 
 defining a p-type metal-oxide-semiconductor field-effect transistor (PMOSFET) over a substrate, the PMOSFET including:    a first source and a first drain, defining a first channel therebetween and each of the first source and first drain comprising p-type dopants, 
 a first gate disposed above the first channel, the first gate comprising a first conducting layer, and  
 a first gate dielectric layer disposed between the first gate and the first channel,  
   wherein the first source and the first drain each comprises compressively strained SiGe having a strain greater than or equal to 0.25%, and the compressively strained SiGe is substantially planar.    
   
   
       49 . The method of  claim 48 , wherein the first channel comprises a first strained semiconductor.  
   
   
       50 . The method of  claim 49 , wherein a Ge content of the compressively strained SiGe is selected from a range of approximately 28% to approximately 100%.  
   
   
       51 . The method of  claim 49 , wherein the compressively strained SiGe has an average roughness height less than 10 nm.  
   
   
       52 . The method of  claim 49 , wherein a strain of the compressively strained SiGe is greater than approximately 1%.  
   
   
       53 . The method of  claim 49 , wherein the substrate consists essentially of silicon.  
   
   
       54 . The method of  claim 49 , further comprising: 
 defining an n-type metal-oxide-semiconductor field-effect transistor (NMOSFET) over the substrate, the NMOSFET including: 
 a second source and a second drain, defining a second channel therebetween and each of the second source and second drain comprising n-type dopants,  
 a second gate disposed above the second channel, the second gate comprising a second conducting layer, and  
 a second gate dielectric layer disposed between the second gate and the second channel,  
   wherein the second channel comprises a second strained semiconductor.    
   
   
       55 . The method of  claim 54 , wherein the second strained semiconductor is tensilely strained.  
   
   
       56 . The method of  claim 55 , wherein the second strained semiconductor comprises silicon.  
   
   
       57 . The method of  claim 56 , wherein the second strained semiconductor consists essentially of silicon.  
   
   
       58 . The method of  claim 56 , wherein the second strained semiconductor is substantially free of germanium.  
   
   
       59 . The method of  claim 56 , wherein the second source and the second drain each comprises a silicon layer substantially free of germanium.  
   
   
       60 . The method of  claim 56 , wherein the PMOSFET and NMOSFET form a complementary metal-oxide-semiconductor (CMOS) device.  
   
   
       61 . The method of  claim 49 , wherein the first strained semiconductor is compressively strained.  
   
   
       62 . The method of  claim 61 , further comprising: 
 defining an n-type metal-oxide-semiconductor field-effect transistor (NMOSFET) over the substrate, the NMOSFET including: 
 a second source and a second drain, defining a second channel therebetween and each of the second source and second drain comprising n-type dopants,  
 a second gate disposed above the second channel, the second gate comprising a second conducting layer, and  
 a second gate dielectric layer disposed between the second gate and the second channel,  
   wherein the second channel comprises a second strained semiconductor.    
   
   
       63 . The method of  claim 62 , wherein the second strained semiconductor is tensilely strained.  
   
   
       64 . The method of  claim 63 , wherein the second strained semiconductor comprises silicon.  
   
   
       65 . The method of  claim 64 , wherein the second strained semiconductor consists essentially of silicon.  
   
   
       66 . The method of  claim 64 , wherein the second strained semiconductor is substantially free of germanium.  67 . The method of  claim 64 , wherein the second source and the second drain each comprises a silicon layer substantially free of germanium.