Pulse-based flip-flop

Abstract

A pulse-based flip-flop that latches a data input signal to convert the data input signal into a data output signal in response to a clock signal. The pulse-based flip-flop comprises a latch that latches the data input signal in response to a first clock pulse signal and a second clock pulse signal and a pulse generator including a NAND gate, a variable delay, and a first inverter, the pulse generator receives the clock signal to generate the first clock pulse signal and the second clock pulse signal. The NAND gate receives the clock signal and an output signal of the variable delay and outputs the second clock pulse signal. The first inverter receives the first clock pulse signal and outputs the second clock pulse signal. The variable delay receives the clock signal and the second clock pulse, and an output signal of the variable delay feeds back to the NAND gate.

1 - 68 . (canceled)  
   
   
       69 . A variable delay comprising: 
 a PMOS transistor having a gate connected to an input signal and a drain connected to a power supply; and    a first NMOS transistor having a drain connected to the source of the PMOS transistor; and    a final output that is a delay of the input signal.    
   
   
       70 . (canceled)  
   
   
       71 . (canceled)  
   
   
       72 . A pulse generator including the variable delay of  claim 69 .  
   
   
       73 . A flip-flop including the pulse generator of  claim 72.