Pulse-based flip-flop

Abstract

A pulse-based flip-flop that latches a data input signal to convert the data input signal into a data output signal in response to a clock signal. The pulse-based flip-flop comprises a latch that latches the data input signal in response to a first clock pulse signal and a second clock pulse signal and a pulse generator including a NAND gate, a variable delay, and a first inverter, the pulse generator receives the clock signal to generate the first clock pulse signal and the second clock pulse signal. The NAND gate receives the clock signal and an output signal of the variable delay and outputs the second clock pulse-signal. The first inverter receives the first clock pulse signal and outputs the second clock pulse signal. The variable delay receives the clock signal and the second clock pulse, and an output signal of the variable delay feeds back to the NAND gate.

1 - 61 . (canceled)  
   
   
       62 . A latch comprising: 
 a first logic circuit for receiving at least one input signal including a second clock pulse and a data input signal;    second logic circuit for receiving an output of the first logic circuit;    a first inverter for receiving a first clock pulse, and an output of the first logic circuit, and outputting a signal sampled for a replica of the first clock pulse and a second output connected to an output of the second logic circuit; and    a second inverter for receiving an output of the first logic circuit and outputting a data output signal synchronized with the delayed first clock pulse and the delayed second clock pulse.    
   
   
       63 . The latch of  claim 62 , wherein the first logic circuit is an inverter.  
   
   
       64 . The latch of  claim 62 , wherein the first logic circuit includes: 
 a first AND gate for receiving the at least one input signal, the at least one input signal including a data input signal and an inverted scan enable signal;    a second AND gate for receiving a scan input signal and a scan enable signal; and    a NOR gate for receiving the outputs of the first and second AND gates, and the first clock pulse.    
   
   
       65 . The latch of  claim 62 , wherein the second logic circuit is an inverter.  
   
   
       66 . The latch of  claim 62 , wherein the second logic circuit is a NAND gate.  
   
   
       67 . The latch of  claim 62 , wherein the second logic circuit is a NOR gate.  
   
   
       68 . The latch of  claim 62 , wherein the second logic circuit is a inverter.  
   
   
       69 - 70 . (canceled)  
   
   
       71 . A flip-flop including the latch of  claim 62 .  
   
   
       72 - 73 . (canceled)