Pulse-based flip-flop

Abstract

A pulse-based flip-flop that latches a data input signal to convert the data input signal into a data output signal in response to a clock signal. The pulse-based flip-flop comprises a latch that latches the data input signal in response to a first clock pulse signal and a second clock pulse signal and a pulse generator including a NAND gate, a variable delay, and a first inverter, the pulse generator receives the clock signal to generate the first clock pulse signal and the second clock pulse signal. The NAND gate receives the clock signal and an output signal of the variable delay and outputs the second clock pulse signal. The first inverter receives the first clock pulse signal and outputs the second clock pulse signal. The variable delay receives the clock signal and the second clock pulse, and an output signal of the variable delay feeds back to the NAND gate.

1 - 24 . (canceled)  
   
   
       25 . A flip-flop that latches a data input signal to convert the data input signal into a data output signal in response to a clock signal, comprising: 
 a latch that latches the data input signal in response to a first clock pulse signal and a second clock pulse signal; and    a pulse generator including a NOR gate, a variable delay, and a first inverter, the pulse generator receives the clock signal to generate the first clock pulse signal and the second clock pulse signal,    wherein the NOR gate receives the clock signal and an output of a variable delay and outputs the first clock pulse signal;    a first inverter for receiving an output of the NOR gate and outputs the second clock pulse signal; and    the variable delay for receiving the clock signal and the second clock pulse signal and feeds the output signal back to the NAND gate.    
   
   
       26 . The flip-flop of  claim 25 , wherein the pulse generator further includes: 
 a second inverter for receiving the output of the variable delay; and    a PMOS transistor having a drain connected to the output of the variable delay, a source connected to a power supply voltage, and a gate for receiving an output of the second inverter.    
   
   
       27 . The flip-flop of  claim 25 , wherein the pulse generator further includes: 
 a second inverter for receiving the output of the variable delay;    a first PMOS transistor having a drain connected to the output of the variable delay, and a gate for receiving the clock signal; and    a second PMOS transistor having a drain connected to a source of the first PMOS transistor, a gate for receiving an output of the second inverter, and a source connected to a power supply voltage.    
   
   
       28 . The flip-flop of  claim 25 , wherein the variable delay includes: 
 a PMOS transistor having a source connected to the power supply voltage, a gate for receiving the clock signal, and a drain connected to the output signal; and    an NMOS transistor having a source connected to the ground voltage, a gate for receiving the second clock pulse signal, and a drain connected to the drain of the PMOS transistor.    
   
   
       29 . The flip-flop of  claim 25 , wherein the variable delay includes: 
 a PMOS transistor having a source connected to a power supply voltage, a gate for receiving the clock signal, and a drain connected to the output signal of the variable delay;    a first NMOS transistor having a gate for receiving a power supply voltage and a drain connected to the drain of the PMOS transistor; and    a second NMOS transistor having a source connected to the ground voltage, a gate for receiving the second clock pulse signal, and a drain connected to a source of the first NMOS transistor.    
   
   
       30 . The flip-flop of  claim 25 , wherein the variable delay includes: 
 a PMOS transistor having a source connected to the power supply voltage and a gate for receiving the clock signal;    an NMOS transistor having a source connected to the ground voltage, a gate for receiving the second clock pulse signal, and a drain connected to a drain of the PMOS transistor;    a third inverter whose input is connected to the drain of the PMOS transistor and the drain of the NMOS transistor; and    a fourth inverter for receiving an output of the third inverter to output an output signal.    
   
   
       31 . The flip-flop of  claim 25 , wherein the variable delay includes: 
 a third inverter for receiving the second clock pulse signal;    a fourth inverter for receiving an output of the third inverter;    a PMOS transistor having a source connected to a power supply voltage, a gate for receiving the clock signal, and a drain connected to the output signal; and    an NMOS transistor having a source connected to a ground voltage, a gate for receiving an output of the fourth inverter, and a drain connected to the output signal.    
   
   
       32 . The flip-flop of  claim 25 , wherein the variable delay includes: 
 a PMOS transistor having a source connected to the power supply voltage, a gate for receiving the clock signal, and a drain connected to the output signal;    a first NMOS transistor having a gate for receiving the second clock pulse signal, and a drain connected to the drain of the PMOS transistor; and    a second NMOS transistor having a gate for receiving the second clock pulse signal, a drain connected to a source of the first NMOS transistor, and a source connected to the ground voltage.    
   
   
       33 . The flip-flop of  claim 25 , wherein the latch includes: 
 a third inverter for receiving the data input signal in response to the first clock pulse signal and the second clock pulse signal;    a fourth inverter for receiving an output of the third inverter;    a fifth inverter for receiving an output of the fourth inverter in response to the first clock pulse signal and the second clock pulse signal, an output of the fifth inverter is connected to the output of the third inverter; and    a sixth inverter for receiving the output of the third inverter to output a data output signal.    
   
   
       34 . The flip-flop of  claim 25 , wherein the latch includes: 
 a first AND gate for receiving the data input signal and an inverted scan enable signal;    a second AND gate for receiving a scan input signal and a scan enable signal;    a NOR gate for receiving outputs of the first and second AND gates in response to the first clock pulse signal and the second clock pulse signal;    a third inverter for receiving an output of the NOR gate;    a fourth inverter for receiving an output of the third inverter in response to the first clock pulse signal and the second clock pulse signal, an output of the fourth inverter is connected to the output of the NOR gate; and    a fifth inverter for receiving the output of the NOR gate to output a data output signal.    
   
   
       35 . The flip-flop of  claim 25 , wherein the latch includes: 
 a third inverter for receiving the data input signal in response to the first clock pulse signal and the second clock pulse signal;    a NAND gate for receiving an output of the third inverter and a set signal;    a fourth inverter for receiving the output signal in response to the first clock pulse signal and the second clock pulse signal, an output of the fourth inverter is connected to the output of the third inverter; and    a fifth inverter for receiving the output of the third inverter to output a data output signal.    
   
   
       36 . The flip-flop of  claim 25 , wherein the latch includes: 
 a third inverter for receiving the data input signal in response to the first clock pulse signal and the second clock pulse signal;    a NOR gate for receiving an output signal of the third inverter and a reset signal;    a fourth inverter for receiving the first clock pulse signal and the second clock pulse signal, an output of the fourth inverter is connected to the output of the third inverter; and    a fifth inverter for receiving the output of the third inverter to output a data output signal.    
   
   
       37 . A flip-flop that latches a data input signal to convert the data input signal into a data output signal in response to a clock signal, comprising: 
 a latch that latches the data input signal in response to the first clock pulse signal and the second clock pulse signal; and    a pulse generator including a NOR gate, a variable delay, and a first inverter, the pulse generator receives the clock signal and an enable signal to generate the first clock pulse signal and the second clock pulse signal,    wherein the NOR gate receives the clock signal, the enable signal and an output of the variabey delay and outputs the first clock pulse signal;    a first inverter for receiving an output of the NOR gate and outputs the second clock pulse signal; and    the variable delay for receiving the clock signal and the second clock pulse signal, and feeds the output signal back to the NAND gate.    
   
   
       38 . The flip-flop of  claim 37 , wherein the pulse generator further includes: 
 a second inverter for receiving the output of the variable delay; and    a PMOS transistor having a drain connected to the output of the variable delay, a source connected to a power supply voltage, and a gate for receiving an output of the second inverter.    
   
   
       39 . The flip-flop of  claim 37 , wherein the pulse generator further includes: 
 a second inverter for receiving the output of the variable delay;    a first PMOS transistor having a drain connected to the output of the variable delay and a gate for receiving the clock signal; and    a second PMOS transistor having a drain connected to the source of the first PMOS transistor, a gate for receiving an output of the second inverter, and a source connected to a power supply voltage.    
   
   
       40 . The flip-flop of  claim 37 , wherein the variable delay includes: 
 a PMOS transistor having a source connected to the power supply voltage, a gate for receiving the clock signal, and a drain connected to the output signal; and    an NMOS transistor having a source connected to the ground voltage, a gate for receiving the second clock pulse signal, and a drain connected to the drain of the PMOS transistor.    
   
   
       41 . The flip-flop of  claim 37 , wherein the variable delay includes: 
 a PMOS transistor having a source connected to the power supply voltage, a gate for receiving the clock signal, and a drain connected to the output signal of the variable delay;    a first NMOS transistor having a gate connected to the power supply voltage and a drain connected to the drain of the PMOS transistor; and    a second NMOS transistor having a source connected to the ground voltage, a gate for receiving the second input signal, and a drain connected to a source of the first NMOS transistor.    
   
   
       42 . The flip-flop of  claim 37 , wherein the variable delay includes: 
 a PMOS transistor having a source connected to the power supply voltage and a gate for receiving the clock signal;    an NMOS transistor having a source connected to the ground voltage, a gate for receiving the second clock pulse signal, and a drain connected to a drain of the PMOS transistor;    a third inverter whose input is connected to the drain of the PMOS transistor and the drain of the NMOS transistor; and    a fourth inverter for receiving an output of the third inverter to output the output signal.    
   
   
       43 . The flip-flop of  claim 37 , wherein the variable delay includes: 
 a third inverter for receiving the second clock pulse signal;    a fourth inverter for receiving an output of the third inverter;    a PMOS transistor having a source connected to the power supply voltage, a gate for receiving the clock signal, and a drain connected to the output signal; and    an NMOS transistor having a source connected to the ground voltage, a gate for receiving the output of the fourth inverter, and a drain connected to the output signal.    
   
   
       44 . The flip-flop of  claim 37 , wherein the variable delay includes: 
 a PMOS transistor having a source connected to a power supply voltage, a gate for receiving the clock signal, and a drain connected to the output signal;    a first NMOS transistor having a gate for receiving the second clock pulse signal and a drain connected to the drain of the PMOS transistor; and    a second NMOS transistor having a gate for receiving the second input signal, a drain connected to a source of the first NMOS transistor, and a source connected to a ground voltage.    
   
   
       45 . The flip-flop of  claim 37 , wherein the latch includes: 
 a third inverter for receiving the data input signal in response to the first clock pulse signal and the second clock pulse signal;    a fourth inverter for receiving an output of the third inverter;    a fifth inverter for receiving the output of the fourth inverter in response to the first clock pulse signal and the second clock pulse signal, an output of the fifth inverter is connected to the output of the third inverter; and    a sixth inverter for receiving the output of the third inverter to output a data output signal.    
   
   
       46 . The flip-flop of  claim 37 , wherein the latch includes: 
 a first AND gate for receiving the data input signal and an inverted scan enable signal;    a second AND gate for receiving a scan input signal and a scan enable signal;    a NOR gate for receiving outputs of the first and second AND gates in response to the first and second clock pulse signals;    a third inverter for receiving an output of the NOR gate;    a fourth inverter for receiving an output of the third inverter in response to the first and second clock pulse signals, an output of the fourth inverter being connected to the output of the NOR gate; and    a fifth inverter for receiving the output of the NOR gate to output the data output signal.    
   
   
       47 . The flip-flop of  claim 37 , wherein the latch includes: 
 a third inverter for receiving the data input signal in response to the first clock pulse signal and the second clock pulse signal;    a NAND gate for receiving the output of the third inverter and a set signal;    a fourth inverter for receiving the output signal in response to the first clock pulse signal and the second clock pulse signal, an output of the fourth inverter is connected to the output of the third inverter; and    a fifth inverter for receiving the output of the third inverter to output the data output signal.    
   
   
       48 . The flip-flop of  claim 37 , wherein the latch includes: 
 a third inverter for receiving the data input signal in response to the first clock pulse signal and the second clock pulse signal;    a NOR gate for receiving an output signal of the third inverter and a reset signal;    a fourth inverter for receiving the first clock pulse signal and the second clock pulse signal, an output of the fourth inverter is connected to the output of the third inverter; and    a fifth inverter for receiving the output of the third inverter to output a data output signal.    
   
   
       49 - 71 . (canceled)