US2007083735A1PendingUtilityA1

Hierarchical processor

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Assignee: GLEW ANDREW FPriority: Aug 29, 2005Filed: Aug 29, 2005Published: Apr 12, 2007
Est. expiryAug 29, 2025(expired)· nominal 20-yr term from priority
Inventors:Andrew F. Glew
G06F 9/3891G06F 9/30167G06F 9/3836G06F 9/3885G06F 9/384G06F 9/3012G06F 9/3838G06F 9/3854G06F 9/3851G06F 9/3858G06F 9/3856
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Claims

Abstract

Various embodiments are described relating to hierarchical processors.

Claims

exact text as granted — not AI-modified
1 . A processor comprising: 
 a plurality of parallel execution clusters, each cluster including one or more execution units; and    a multilevel instruction scheduler, including: 
 a plurality of first instruction schedulers, a first instruction scheduler provided for each execution cluster; and  
 a second instruction scheduler common to the plurality of execution clusters.

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