Low-voltage single-layer polysilicon eeprom memory cell

Abstract

The present invention is an electronic memory cell and a method for the cell's fabrication comprising a The first transistor configured to be coupled to a bit line. The first transistor has an essentially zero voltage drop when activated and is configured to control an operation of the memory cell. A second transistor is configured to operate as a memory transistor and is coupled to the first transistor. The second transistor is further configured to be programmable with a voltage about equal to a voltage on the bit line.

1 . A method for writing to an electronic programmable memory cell, comprising: 
 applying about 10 volts to a source of a select transistor;    applying 0 volts to a gate of the select transistor;    applying 0 volts to a gate of a memory transistor; and    allowing a source terminal of a memory transistor to float.