System and method for analyzing software performance without requiring hardware

Abstract

A system and method for analyzing software performance without requiring hardware is presented. A timing description generator logs instruction performance characteristics for each of the assembly code's instructions. The performance characteristics identify whether an instruction issued or stalled during particular instruction cycles. Once the timing description generator cycles through the instructions and logs performance characteristics for each instruction, the timing description generator generates a performance graph. For each page line, the performance graph includes 1) dual-issue information if applicable, 2) instruction cycle counter values/stalled instruction identifier's that are positioned at corresponding line location values, and 3) the instruction. A developer may analyze the performance graph and identify code locations that require optimization in order to increase performance.

1 . A computer-implemented method comprising: 
 retrieving an instruction;    determining whether the instruction is ready to execute;    storing performance characteristics that include an instruction cycle counter value and a line location value in response to determining that the instruction is ready to execute;    storing performance characteristics that include a stalled instruction identifier and the line location value in response to determining that the instruction is not ready to execute; and    generating a performance graph using the performance characteristics.    
   
   
       2 . The method of  claim 1  further comprising: 
 wherein the instruction cycle counter value corresponds to an instruction cycle and the line location value corresponds to a line position on a page line to display the instruction cycle counter value.    
   
   
       3 . The method of  claim 1  further comprising: 
 executing one instruction cycle; and    incrementing the instruction cycle counter and the line location value.    
   
   
       4 . The method of  claim 3  further comprising: 
 determining that the instruction is not complete; and    storing the incremented instruction cycle counter and the incremented line location value in response to determining that the instruction is not complete.    
   
   
       5 . The method of  claim 1  further comprising: 
 detecting a pipeline identifier corresponding to the instruction, the pipeline identifier corresponding to a pipeline that is included in a plurality of pipelines;    storing the pipeline identifier in response to the detecting; and    wherein the generated performance graph includes the pipeline identifier.    
   
   
       6 . The method of  claim 1  further comprising: 
 identifying that the instruction is eligible for dual-issue;    determining whether the instruction is prevented from dual-issuing in response to the identifying;    storing a dual-issue prevented identifier in response to determining that the instruction is prevented from dual-issuing;    storing a dual-issue allowed identifier in response to determining that the instruction is not prevented from dual-issuing; and    wherein the generated performance graph includes the dual-issue prevented identifier or the dual-issue allowed identifier.    
   
   
       7 . The method of  claim 1  wherein the performance graph includes a page line corresponding to the instruction, the page line including the instruction, the instruction cycle counter value at the line location value, a dual-issue prevented symbol or a dual-issue allowable symbol, and a pipeline identifier.  
   
   
       8 . A computer program product comprising: 
 a computer operable medium having computer readable code, the computer readable code being effective to: 
 retrieve an instruction;  
 determine whether the instruction is ready to execute;  
 store performance characteristics that include an instruction cycle counter value and a line location value in response to determining that the instruction is ready to execute;  
 store performance characteristics that include a stalled instruction identifier and the line location value in response to determining that the instruction is not ready to execute; and  
 generate a performance graph using the performance characteristics.  
   
   
   
       9 . The computer program product of  claim 8  wherein the instruction cycle counter value corresponds to an instruction cycle and the line location value corresponds to a line position on a page line to display the instruction cycle counter value.  
   
   
       10 . The computer program product of  claim 8  wherein the computer readable code is further effective to: 
 execute one instruction cycle; and    increment the instruction cycle counter and the line location value.    
   
   
       11 . The computer program product of  claim 10  wherein the computer readable code is further effective to: 
 determine that the instruction is not complete; and    store the incremented instruction cycle counter and the incremented line location value in response to determining that the instruction is not complete.    
   
   
       12 . The computer program product of  claim 8  wherein the computer readable code is further effective to: 
 detect a pipeline identifier corresponding to the instruction, the pipeline identifier corresponding to a pipeline that is included in a plurality of pipelines;    store the pipeline identifier in response to the detecting; and    wherein the generated performance graph includes the pipeline identifier.    
   
   
       13 . The computer program product of  claim 8  wherein the computer readable code is further effective to: 
 identify that the instruction is eligible for dual-issue;    determine whether the instruction is prevented from dual-issuing in response to the identifying;    store a dual-issue prevented identifier in response to determining that the instruction is prevented from dual-issuing;    store a dual-issue allowed identifier in response to determining that the instruction is not prevented from dual-issuing; and    wherein the generated performance graph includes the dual-issue prevented identifier or the dual-issue allowed identifier.    
   
   
       14 . The computer program product of  claim 8  wherein the performance graph includes a page line corresponding to the instruction, the page line including the instruction, the instruction cycle counter value at the line location value, a dual-issue prevented symbol or a dual-issue allowable symbol, and a pipeline identifier.  
   
   
       15 . An information handling system comprising: 
 one or more processors;    a memory accessible by the processors;    one or more nonvolatile storage devices accessible by the processors; and    a performance graph generation tool for generating a performance graph, the performance graph generation tool being effective to: 
 retrieve an instruction from one of the nonvolatile storage devices;  
 determine whether the instruction is ready to execute;  
 store performance characteristics in one of the nonvolatile storage devices that include an instruction cycle counter value and a line location value in response to determining that the instruction,is ready to execute;  
 store performance characteristics in one of the nonvolatile storage devices that include a stalled instruction identifier and the line location value in response to determining that the instruction is not ready to execute; and  
 generate a performance graph using the performance characteristics.  
   
   
   
       16 . The information handling system of  claim 15  wherein the instruction cycle counter value corresponds to an instruction cycle and the line location value corresponds to a line position on a page line to display the instruction cycle counter value.  
   
   
       17 . The information handling system of  claim 15  wherein the performance graph generation tool is further effective to: 
 execute one instruction cycle; and    increment the instruction cycle counter and the line location value.    
   
   
       18 . The information handling system of  claim 17  wherein the performance graph generation tool is further effective to: 
 determine that the instruction is not complete; and    store the incremented instruction cycle counter and the incremented line location value in one of the nonvolatile storage devices in response to determining that the instruction is not complete.    
   
   
       19 . The information handling system of  claim 15  wherein the performance graph generation tool is further effective to: 
 detect a pipeline identifier corresponding to the instruction, the pipeline identifier corresponding to a pipeline that is included in a plurality of pipelines;    store the pipeline identifier in one of the nonvolatile storage devices in response to the detecting; and    wherein the generated performance graph includes the pipeline identifier.    
   
   
       20 . The information handling system of  claim 15  wherein the performance graph generation tool is further effective to: 
 identify that the instruction is eligible for dual-issue;    determine whether the instruction is prevented from dual-issuing in response to the identifying;    store a dual-issue prevented identifier in one of the nonvolatile storage devices in response to determining that the instruction is prevented from dual-issuing;    store a dual-issue allowed identifier in one of the nonvolatile storage devices in response to determining that the instruction is not prevented from dual-issuing; and    wherein the generated performance graph includes the dual-issue prevented identifier or the dual-issue allowed identifier.