Recess channel transistor for preventing deterioration of device characteristics due to misalignment of gate layers and method of forming the same

Abstract

The recess channel transistor includes: a semiconductor substrate including a device insulation layer defining an activation region in which recesses are formed; insulation buffer patterns, each of which is formed at an opening of the recess on a surface of the substrate; gates, each of which includes a recess gate formed in the recess and a top gate formed on the substrate; spacers, each of which is formed at both sides of the gate; and a source region and a drain region formed at both sides of each gate on the surface of the substrate, where the source and drain regions have an even doping profile due to the existence of insulation buffer patterns. Accordingly, characteristics of the transistor can be prevented from deteriorating due to misalignment of the top gate with the recess gate.

1 . A recess channel transistor comprising: 
 a semiconductor substrate having a device insulation layer defining an activation region in which recesses, each having sidewalls, are formed to a predetermined depth below the surface of the semiconductor substrate;    an insulation buffer pattern formed in a upper portion of each sidewall in each recess, wherein the upper portion of each sidewall in each recess adjoins the surface of the semiconductor substrate;    a gate comprising a top gate and a recess gate formed in each recess, wherein the recess gate is formed inside each recess and the top gate is formed on the recess gate;    a source region formed on the surface of the semiconductor substrate on one side of the gate, and a drain region formed on the surface of the semiconductor substrate on another side of the gate    wherein the source and drain regions have even doping profile due to the existence of insulation buffer patterns.    
   
   
       2 . The recess channel transistor as claimed in  claim 1 , wherein the insulation buffer patterns are made of a nitride layer or a nitric oxide layer.  
   
   
       3 . The recess channel transistor as claimed in  claim 1 , wherein the insulation buffer patterns are formed to a depth of 100˜300 Å measured from the surface of the semiconductor substrate.  
   
   
       4 . The recess channel transistor as claimed in  claim 1 , wherein the insulation buffer patterns are formed to a width of 50˜500 Å measured from one side wall to another sidewall of the recess.  
   
   
       5 . The recess channel transistor as claimed in  claim 1 , wherein each recess gate is formed to a depth of 500˜1000 Å measured from the surface of the semiconductor substrate.  
   
   
       6 . The recess channel transistor as claimed in  claim 1 , wherein a hard mask layer is formed on each top gate and wherein a spacer is formed on each side of each gate having the top gate and the recess gate.  
   
   
       7 . A method of forming a recess channel transistor in a semiconductor substrate having an activation region defined by adjoining device insulation regions, the method comprising the steps of: 
 etching gate forming portions in the activation region, so as to form first recesses;    etching the device insulation regions, so as to form trenches;    filling each trenche and each first recess with an insulation layer;    etching a center portion of the insulation layer filled inside each first recess and continue etching the semiconductor substrate under the etched center portion of the insulation layer, so as to make second recesses that are deeper than the first recesses, wherein the unetched portions outside the etched center portion of the insulation layer remaining at near the opening of each second recess forms insulation buffer patterns;    forming a gate insulation layer on an inner wall of each second recess, excluding the surface of the insulation buffer patterns;    forming a gate conductive layer on the whole surface of the substrate having the second recesses and the insulation buffer patterns;    etching the gate conductive layer, so as to form the gates such that each gate comprises a recess gate formed inside one second recess and a top gate formed on the recess gate;    forming spacers at both sidewalls of each gate; and    performing source/drain ion implant on the resultant of the substrate, so as to form a source region and a drain region at both sides of each gate in the substrate,    wherein the source and drain regions have an even doping profile due to an existence of insulation buffer patterns.    
   
   
       8 . The method of forming a recess channel transistor as claimed in  claim 7 , wherein each of the first recesses is formed at a depth of 100˜300 Å measured from the surface of the semiconductor substrate.  
   
   
       9 . The method of forming a recess channel transistor as claimed in  claim 7 , wherein each of the second recesses is formed at a depth of 500˜1000 Å measured from the surface of the semiconductor substrate.  
   
   
       10 . The method of forming a recess channel transistor as claimed in  claim 7 , wherein the insulation buffer patterns are formed of a nitride layer or a nitric oxide layer.  
   
   
       11 . The method of forming a recess channel transistor as claimed in  claim 7 , wherein the insulation buffer patterns are formed to a depth of 100˜300 Å measured from the surface of the substrate.  
   
   
       12 . The method of forming a recess channel transistor as claimed in  claim 7 , wherein each insulation buffer pattern is formed to a width of 50˜500 Å measured from the inner surface of the second recess.  
   
   
       13 . The method of forming a recess channel transistor as claimed in  claim 7 , the step of etching the gate conductive layer comprising the substep of: 
 forming a hard mask layer on the gate conductive layer prior to etching.    
   
   
       14 . A method of forming a recess channel transistor in a semiconductor substrate having an activation region defined by adjoining device insulation regions, the method comprising the steps of: 
 etching gate forming portions in the activation region, so as to form first recesses;    forming an insulation layer on the entire surface of the substrate including the first recesses;    blanket etching the insulation layer, so as to form insulation buffer patterns on the sidewalls of each first recess;    etching a bottom surface of each first recess exposed between the insulation buffer patterns, so as to make a second recess deeper than the first recess;    forming a gate insulation layer on the surface of each of the second recesses, excluding the surface of the insulation buffer patterns;    forming a gate conductive layer on the entire surface of the substrate having the second recesses and insulation buffer patterns formed thereon, so that the second recesses including the gate insulation layer are filled with the gate conductive layer;    etching the gate conductive layer, so as to form the gates such that each gate comprises a recess gate formed inside one second recess and a top gate formed on the recess gate;    forming spacers at both sidewalls of the gates; and    performing source/drain ion implant on the resultant of the substrate, so as to form source and drain regions at both sides of each gate in the substrate,    wherein the source and drain regions have an even doping profile due to the existence of insulation buffer patterns.    
   
   
       15 . The method of forming a recess channel transistor as claimed in  claim 14 , wherein each of the first recesses is formed to a depth of 100˜300 Å measured from the surface of the substrate.  
   
   
       16 . The method of forming a recess channel transistor as claimed in  claim 14 , wherein the insulation buffer patterns are formed of a nitride layer or a nitric oxide layer.  
   
   
       17 . The method of forming a recess channel transistor as claimed in  claim 14 , wherein each of the insulation buffer patterns is formed to a depth of 100˜300 Å measured from the surface of the substrate.  
   
   
       18 . The method of forming a recess channel transistor as claimed in  claim 14 , wherein each of the insulation buffer patterns is formed to a width of 50˜500 Å measured from the inner surface of the second recesses.  
   
   
       19 . The method of forming a recess channel transistor as claimed in  claim 14 , wherein each of the second recesses is formed to a depth of 500˜1000 Å measured from the surface of the substrate.  
   
   
       20 . The method of forming a recess channel transistor as claimed in  claim 14 , the step of etching the gate conductive layer comprising the substep of: 
 forming a hard mask layer on the gate conductive layer prior to etching.