Method of selective post-growth tuning of an optical bandgap of a semi-conductor heterostructure and products produced thereof

Abstract

A method of controlling the degree of IFVEI for post-growth tuning of an optical bandgap of a semiconductor heterostructure. The resultant layer structure may contain a semi-conductor heterostructure with one or more regions with selectively modified bandgap. According to one aspect of the invention, a metal interlayer is deposited between the heterostructure and a dielectric layer such as silica. According to another aspect of the invention, an oxidized surface is provided between a dielectric layer and the heterostructure. The presence of the oxide layer improves stability and reproducibility in the post-annealing process. In a further aspect, the oxide layer may be provided between the interlayer and the heterostructure. In one embodiment of the invention, a photoresist mask with a specific pattern is deposited on the surface of the heterostructure so that the interlayer is deposited in an unmasked region whereon post-growth tuning results. In another embodiment, multiple photolithography is performed to deposit interlayers of varying thickness and/or regions on the heterostructure, followed by thermal post-annealing of the dielectric layer. This method produces heterostructures with optical bandgaps having selectively tuned regions.

1 . A layer structure comprising: 
 a semi-conductor heterostructure;    at least one metallic interlayer deposited next to at least one surface and in at least one region of said semiconductor heterostructure; and    a dielectric layer coated next to said at least one metallic interlayer.    
   
   
       2 . A layer structure according to  claim 1 , wherein only one surface is deposited with said at least one metallic interlayer.  
   
   
       3 . A layer structure according to  claim 1 , wherein only the top surface is deposited with said at least one metallic interlayer.  
   
   
       4 . A layer structure according to  claim 1 , further comprising an oxide layer between said semiconductor heterostructure and said at least one metallic interlayer.  
   
   
       5 . A layer structure according to  claim 2  further comprising an oxide layer between said semiconductor heterostructure and said at least one metallic interlayer.  
   
   
       6 . A layer structure according to  claim 2 , wherein said semiconductor heterostructure is a single quantum well structure, a multiple quantum well structure, a superlattice structure or a quantum dot structure.  
   
   
       7 . A layer structure according to  claim 2 , wherein said semiconductor heterostructure comprises: 
 a As/GaAs quantum well structure having a plurality of alternating AlGaAs and GaAs layers; or    an InGaAs/GaAs quantum well structure having a plurality of alternating InGaAs and GaAs layers.    
   
   
       8 . A layer structure according to  claim 2 , wherein said at least one metallic interlayer comprises a single layer of metal, a single layer of alloyed metal, multiple layers of metal, multiple layers of alloyed metal, or multiple layers of metal and alloyed metal.  
   
   
       9 . A layer structure according to  claim 2 , wherein said at least one metallic interlayer is 1 to 10,000 angstrom thick.  
   
   
       10 . A layer structure according to  claim 2 , wherein said at least one metallic interlayer is 10 to 500 angstrom thick.  
   
   
       11 . A layer structure according to  claim 2 , wherein a plurality of metallic interlayers are deposited in different regions of said semiconductor heterostructure.  
   
   
       12 . A layer structure according to  claim 2 , wherein a plurality of metallic interlayers are deposited in different regions of said semiconductor heterostructure, and at least two of said metallic interlayers have different thicknesses.  
   
   
       13 . A layer structure according to  claim 2 , wherein said dielectric layer is made from silica oxide or silica.  
   
   
       14 . A layer structure according to  claim 5 , wherein said semiconductor heterostructure is a single quantum well structure, a multiple quantum well structure, a superlattice structure or a quantum dot structure.  
   
   
       15 . A layer structure according to  claim 5 , wherein said semiconductor heterostructure comprises: 
 a AlGaAs/GaAs quantum well structure having a plurality of alternating AlGaAs and GaAs layers; or    an InGaAs/GaAs quantum well structure having a plurality of alternating InGaAs and GaAs layers.    
   
   
       16 . A layer structure according to  claim 5 , wherein said at least one metallic interlayer comprises a single layer of metal, a single layer of alloyed metal, multiple layers of metal, multiple layers of alloyed metal, or multiple layers of metal and alloyed metal.  
   
   
       17 . A layer structure according to  claim 5 , wherein said at least one metallic interlayer is 1 to 10,000 angstrom thick.  
   
   
       18 . A layer structure according to  claim 5 , wherein said at least one metallic interlayer is 10 to 500 angstrom thick.  
   
   
       19 . A layer structure according to  claim 5 , wherein a plurality of metallic interlayers are deposited in different regions of said semiconductor heterostructure.  
   
   
       20 . A layer structure according to  claim 5 , wherein a plurality of metallic interlayers are deposited in different regions of said semiconductor heterostructure, and at least two of said metallic interlayers have different thicknesses.  
   
   
       21 . A layer structure according to  claim 5 , wherein said semiconductor heterostructure is made from elements from column III to V of the periodic table of elements.  
   
   
       22 . A layer structure according to  claim 5 , wherein said dielectric layer is made from silica oxide or silica.  
   
   
       23 . A layer structure comprising: 
 a semi-conductor heterostructure;    at least one oxide layer formed on at least one surface of said semiconductor heterostructure; and    a dielectric layer coated next to said oxide layer.    
   
   
       24 . A layer structure according to  claim 23 , wherein said at least one oxide layer is formed by the oxidation of said surface of said semiconductor heterostructure.