High performance lateral bipolar transistor

Abstract

A lateral bipolar transistor comprises an emitter region, a base region, a collector region, and a gate disposed over the base region. A bias line is connected to the gate for applying a bias voltage thereto during operation of the transistor. The polarity of the bias voltage is such as to create an accumulation layer in the base under the gate. The accumulation layer provides a low-resistance path for the transistor base current, thus reducing the base resistance of the transistor.

1 .- 25 . (canceled)  
   
   
       26 . A method of operating a lateral bipolar transistor fabricated in a layer of silicon on insulator on a semiconductor substrate, said transistor including: 
 an emitter region, a collector region, and a base region, said base region being confined in a space between said emitter and collector regions and said insulator, and    a gate disposed over said base region;    said method comprising applying a bias potential to said gate to generate an accumulation layer in said base region under said gate, thereby reducing a base resistance of said transistor.    
   
   
       27 . A method of operating a lateral bipolar transistor, said transistor including: 
 an emitter region, a collector region, and a base finger, said emitter and collector regions being arranged on opposite longitudinal sides of said base finger, a base contact positioned on a longitudinal extension of said base finger outside a space between said emitter and collector regions, and    a gate disposed over said base finger;    said method comprising applying a bias potential to said gate to generate an accumulation layer in said base finger under said gate, thereby reducing a base resistance of said transistor.    
   
   
       28 . A method of operating a lateral bipolar transistor, said transistor including: 
 an emitter region, a collector region and a base structure, said base structure comprising a base portion in a space between said emitter and collector regions,    a base contact positioned on a surface of said base structure such that a base current flowing in said base structure has a substantial component flowing laterally in said base portion, and    a gate disposed over said base portion;    said method comprising applying a bias potential to said gate to generate an accumulation layer in said base portion under said gate, thereby reducing a base resistance of said transistor.    
   
   
       29 . The method of  claim 26  wherein said emitter region is formed as a heavily doped region.  
   
   
       30 . The method of  claim 26  wherein said collector region is formed by a lightly doped sub-region and a heavily doped sub-region.  
   
   
       31 . The method of  claim 26  wherein said lateral bipolar transistor is a npn-type transistor and said bias potential is a negative potential.  
   
   
       32 . The method of  claim 26  wherein said lateral bipolar transistor is a pnp-type transistor and said bias potential is a positive potential.  
   
   
       33 . The method of  claim 26  wherein at least one of said emitter region, said collector region and said gate comprises a surface layer of silicide.  
   
   
       34 . The method of  claim 27  wherein said emitter region is formed as a heavily doped region.  
   
   
       35 . The method of  claim 27  wherein said collector region is formed by a lightly doped sub-region and a heavily doped sub-region.  
   
   
       36 . The method of  claim 27  wherein said lateral bipolar transistor is a npn-type transistor and said bias potential is a negative potential.  
   
   
       37 . The method of  claim 27  wherein said lateral bipolar transistor is a pnp-type transistor and said bias potential is a positive potential.  
   
   
       38 . The method of  claim 27  wherein at least one of said emitter region, said collector region and said gate comprises a surface layer of silicide.  
   
   
       39 . The method of  claim 28  wherein said emitter region is formed as a heavily doped region.  
   
   
       40 . The method of  claim 28  wherein said collector region is formed by a lightly doped sub-region and a heavily doped sub-region.  
   
   
       41 . The method of  claim 28  wherein said lateral bipolar transistor is a npn-type transistor and said bias potential is a negative potential.  
   
   
       42 . The method of  claim 28  wherein said lateral bipolar transistor is a pnp-type transistor and said bias potential is a positive potential.  
   
   
       43 . The method of  claim 28  wherein at least one of said emitter region, said collector region and said gate comprises a surface layer of silicide.