Transistor, meomory cell array and method of manufacturing a transistor

Abstract

A transistor, memory cell array and method of manufacturing a transistor are disclosed. In one embodiment, the invention refers to a transistor, which is formed at least partially in a semiconductor substrate, comprising a first and a second source/drain regions, a channel region connecting said first and second source/drain regions, said channel region being disposed in said semiconductor substrate, and a gate electrode disposed along said channel region and being electrically isolated from said channel region, for controlling an electrical current flowing between said first and second source/drain regions, wherein said channel region comprises a fin-region in which the channel has the shape of a ridge, said ridge comprising a top side and two lateral sides in a cross section perpendicular to a line connecting said first and second source/drain regions, wherein said top side is disposed beneath a surface of said semiconductor substrate and said gate electrode is disposed along said top side and said two lateral sides.

1 . A transistor, suitable for use in a DRAM cell, said transistor being formed at least partially in a semiconductor substrate, comprising: 
 a first source/drain region;    a first contact region which is adapted to connect said first source/drain region with an electrode of a storage capacitor;    a second source/drain region;    a second contact region which is adapted to connect said second source/drain region with a bitline;    a channel region connecting said first and second source/drain regions, said channel region being disposed in said semiconductor substrate, a first direction being defined by a line connecting said first and second source/drain regions; and    a gate electrode disposed along said channel region and being electrically isolated from said channel region by a gate isolating layer, said gate electrode controlling an electrical current flowing between said first and second source/drain regions, wherein said channel region comprises a fin-region in which said channel region has the shape of a ridge and in which the gate electrode is disposed at three sides of the channel region, wherein a current path connecting said first and second contact regions comprises a first vertical region in which the direction of said current has a component in a first vertical direction, a horizontal region in which the direction of said current has a horizontal component, and a second vertical region in which the direction of said current has a component in a second vertical direction, said first vertical direction being opposed to said second vertical direction.    
     
     
         2 . The transistor according to  claim 1 , further comprising a spacer made from an isolating material, said spacer being arranged at an interface between said gate electrode and said first and second vertical regions of said current path and having a thickness larger than that of said gate isolating layer.  
     
     
         3 . The transistor according to  claim 1 , wherein said first and second source/drain regions are arranged within said first and second vertical regions, respectively.  
     
     
         4 . The transistor according to  claim 1 , wherein the width of said channel region is smaller than the width of said first or second source/drain regions, the width being measured in a direction perpendicular to said first direction and parallel to a surface of said semiconductor substrate.  
     
     
         5 . A transistor, suitable for use in a DRAM cell, said transistor being formed at least partially in a semiconductor substrate, comprising: 
 a first source/drain region which is adapted to be connected with an electrode of a storage capacitor;    a second source/drain region which is adapted to be connected with a bitline;    a channel region connecting said first and second source/drain regions, said channel region being disposed in said semiconductor substrate, a first direction being defined by a line connecting said first and second source/drain regions; and    a gate electrode disposed along said channel region and being electrically isolated from said channel region by a gate isolating layer, said gate electrode controlling an electrical current flowing between said first and second source/drain regions, wherein said channel region comprises a fin-region in which the channel has the shape of a ridge, said ridge comprising a top side and two lateral sides in a cross section perpendicular to said first direction, wherein said top side is disposed beneath a surface of said semiconductor substrate and said gate electrode is disposed along said top side and said two lateral sides.    
     
     
         6 . The transistor according to  claim 5 , wherein the distance between said top side and said substrate surface, measured in a direction perpendicular to said substrate surface, is 10 to 200 nm.  
     
     
         7 . The transistor according to  claim 5 , further comprising a spacer made from an isolating material, said spacer being arranged at an interface between said gate electrode and said first and second source/drain regions.  
     
     
         8 . The transistor according to  claim 5 , wherein said first source/drain region comprises a heavily doped and a lightly doped region, said lightly doped region being disposed between said heavily doped region and said channel region.  
     
     
         9 . The transistor according to  claim 8 , wherein said lightly doped region extends to a depth beneath said top side of said fin region.  
     
     
         10 . The transistor according to  claim 9 , further comprising a spacer made from an isolating material, said spacer being arranged at an interface between said gate electrode and said first and second source/drain regions.  
     
     
         11 . The transistor according to  claim 10 , wherein said heavily doped region is disposed above said lightly doped region and said spacer extends to a depth corresponding to the depth of said heavily doped region.  
     
     
         12 . The transistor according to  claim 5 , wherein said first source/drain region extends to the same depth as the second source/drain region.  
     
     
         13 . The transistor according to  claim 7 , wherein the isolating material of said spacer is selected from the group consisting of silicon dioxide and silicon nitride.  
     
     
         14 . The transistor according to  claim 5 , wherein the width of said channel region is smaller than the width of said first or second source/drain regions, wherein the width is measured in a direction perpendicular to said first direction and parallel to said surface of said semiconductor substrate.  
     
     
         15 . A memory cell array comprising a plurality of memory cells, a plurality of bitlines which are arranged in a first direction and a plurality of wordlines which are arranged in a second direction intersecting said first direction,  
       each of said memory cells comprising: 
 a storage capacitor;  
 a transistor which is at least partially formed in a semiconductor substrate said transistor comprising;  
 a first source/drain region which is connected with an electrode of said storage capacitor;  
 a second source/drain region;  
 a channel region connecting said first and second doped regions, said channel region being disposed in said semiconductor substrate; and  
 a gate electrode disposed along said channel region and being electrically isolated from said channel region, said gate electrode controlling an electrical current flowing between said first and second source/drain regions,  
 wherein said channel region comprises a fin-region in which the channel assumes the shape of a ridge, said ridge comprising a top side and two lateral sides in a cross section perpendicular to a line connecting said first and second source/drain regions, wherein said top side is disposed beneath a surface of said semiconductor substrate and said gate electrode is disposed along said top side and said two lateral sides, wherein each of said wordlines is electrically connected with a plurality of gate electrodes, and wherein said second source/drain region of each of said transistors is connected with one of said bitlines via a bitline contact.  
 
     
     
         16 . The memory cell array according to  claim 15 , wherein said storage capacitor is a trench capacitor.  
     
     
         17 . The memory cell array according to  claim 15 , wherein said storage capacitor is a stacked capacitor.  
     
     
         18 . The memory cell array according to  claim 15 , wherein said memory cells are disposed in rows and columns, respectively, and said storage capacitors and said transistors are arranged in a checkerboard pattern so that said transistors are related to first sites and said storage capacitors are related to second sites, one of said first sites being disposed between two of said second sites and vice versa.  
     
     
         19 . The memory cell array according to  claim 15 , wherein said memory cells are disposed in rows and columns, respectively, and said storage capacitors and said transistors are arranged in pairs so that two storage capacitors are arranged adjacent to each other and two transistors are adjacent to each other and two neighbouring memory cells share a common bitline contact.  
     
     
         20 . The memory cell array according to  claim 15 , wherein each of said wordlines comprises a plurality of passing wordline portions in which the wordline is not connected with a gate electrode, said passing wordline portions being disposed at a depth of said substrate which is smaller than a depth of said gate electrodes.  
     
     
         21 . The memory cell array according to  claim 15 , wherein each of said wordlines comprises a plurality of passing wordline portions in which the wordline is not connected with a gate electrode, said passing wordline portions being disposed on the substrate surface.  
     
     
         22 - 29 . (canceled)  
     
     
         30 . A transistor comprising: 
 a first source/drain region;    a second source/drain region;    a channel region between the first and second source/drain regions; and    a gate electrode,    wherein the channel region comprises a fin-region in the shape of a ridge, the ridge comprising a top side and two lateral sides, the top side disposed beneath a surface of a semiconductor substrate and the gate electrode disposed along the top side and the two lateral sides.    
     
     
         31 . The transistor of  claim 30 , further comprising: 
 a spacer between the gate electrode and the first and second source/drain regions.    
     
     
         32 . The transistor of  claim 30 , wherein the first source/drain region comprises a heavily doped and a lightly doped region, the lightly doped region between the heavily doped region and the channel region.  
     
     
         33 . The transistor of  claim 32 , wherein the lightly doped region extends below the top side of the fin-region.  
     
     
         34 . The transistor of  claim 33 , further comprising: 
 a spacer between the gate electrode and the first and second source/drain regions.    
     
     
         35 . The transistor of  claim 34 , wherein the heavily doped region is above the lightly doped region and the spacer extends to a depth corresponding to a depth of the heavily doped region.  
     
     
         36 . The transistor of  claim 30 , wherein the first source/drain region extends to a same depth as the second source/drain region.