Semiconductor memory device and method of manufacturing the same

Abstract

A semiconductor memory device includes first and second element isolation insulating films, first and second gate insulating films, first and second gate wiring and first and second mask layer. First and second upper surfaces of the first and second element isolation insulating films are higher than an upper surface of the substrate, first and second bottom surfaces of the first and second element isolation insulating films are lower than the upper surface of the substrate, a second height from the upper surface of the substrate to the second upper surface is larger than a first height from the upper surface of the substrate to the first upper surface. A height from the upper surface of the substrate to an upper surface of the first mask layer equals a height from the upper surface of the substrate to an upper surface of the second mask layer.

1 . A semiconductor memory device comprising: 
 a semiconductor substrate which has a first region and a second region;    a first element isolation insulating film which is formed in the semiconductor substrate in the first region, includes a first upper surface higher than an upper surface of the semiconductor substrate and a first bottom surface lower than the upper surface of the semiconductor substrate, and has a first height from the upper surface of the semiconductor substrate to the first upper surface;    a second element isolation insulating film which is formed in the semiconductor substrate in the second region, includes a second upper surface higher than the upper surface of the semiconductor substrate and a second bottom surface lower than the upper surface of the semiconductor substrate, and has a second height from the upper surface of the semiconductor substrate to the second upper surface, the second height being larger than the first height;    a first gate insulating film which is formed on the semiconductor substrate in the first region;    a first gate wiring which is formed on the first gate insulating film;    a first mask layer which is formed on the first gate wiring;    a second gate insulating film which is formed on the semiconductor substrate in the second region;    a second gate wiring which is formed on the second gate insulating film; and    a second mask layer which is formed on the second gate wiring,    wherein a height from the upper surface of the semiconductor substrate to an upper surface of the first mask layer equals a height from the upper surface of the semiconductor substrate to an upper surface of the second mask layer.    
   
   
       2 . The device according to  claim 1 , wherein the first element isolation insulating film has a first depth from the upper surface of the semiconductor substrate to the first bottom surface, the second element isolation insulating film has a second depth from the upper surface of the semiconductor substrate to the second bottom surface, and the second depth is larger than the first depth.  
   
   
       3 . The device according to  claim 2 , wherein the first depth is larger than the first height, and the second depth is larger than the second height.  
   
   
       4 . The device according to  claim 1 , wherein a thickness of the second mask layer is larger than a thickness of the first mask layer.  
   
   
       5 . The device according to  claim 1 , wherein a thickness of the second mask layer equals a thickness of the first mask layer.  
   
   
       6 . The device according to  claim 1 , which further comprises: 
 a first silicide layer which is provided between the first gate wiring and the first mask layer and has a first thickness; and    a second silicide layer which is provided between the second gate wiring and the second mask layer and has a second thickness equal to the first thickness, and    in which a thickness of the first gate wiring is larger than a thickness of the second gate wiring.    
   
   
       7 . The device according to  claim 1 , which further comprises: 
 a first silicide layer which is provided between the first gate wiring and the first mask layer and has a first thickness; and    a second silicide layer which is provided between the second gate wiring and the second mask layer and has a second thickness equal to the first thickness, and    in which a thickness of the first gate wiring equals a thickness of the second gate wiring.    
   
   
       8 . The device according to  claim 1 , wherein 
 the first element isolation insulating film has a first portion including the first upper surface and the first bottom surface, and a second portion including a third upper surface flush with the upper surface of the semiconductor substrate and a third bottom surface flush with the first bottom surface,    the second element isolation insulating film has a third portion including the second upper surface and the second bottom surface, and a fourth portion including a fourth upper surface flush with the upper surface of the semiconductor substrate and a fourth bottom surface flush with the second bottom surface,    the first portion is located below the first gate wiring, and the second portion is located except below the first gate wiring, and    the third portion is located below the second gate wiring, and the fourth portion is located except below the second gate wiring.    
   
   
       9 . The device according to  claim 1 , which further comprises: 
 a first diffusion layer which is formed in the semiconductor substrate in the first region; and    a second diffusion layer which is formed in the semiconductor substrate in the second region, and    in which the first depth has a level lower than a bottom surface of the first diffusion layer, and the second depth has a level lower than a bottom surface of the second diffusion layer.    
   
   
       10 . The device according to  claim 1 , further comprising: 
 a first contact which is arranged above the first element isolation insulating film and connected to the first gate wiring, and    a second contact which is arranged above the second element isolation insulating film and connected to the second gate wiring.    
   
   
       11 . The device according to  claim 1 , wherein a thickness of the first gate wiring is smaller than a thickness of the second gate wiring.  
   
   
       12 . The device according to  claim 1 , wherein 
 the first region is a memory cell region, and the second region is a peripheral circuit region, and    the first gate wiring has a floating gate electrode provided on the first gate insulating film, a control gate electrode provided above the floating gate electrode, and an insulating film provided between the floating gate electrode and the control gate electrode.    
   
   
       13 . A semiconductor memory device manufacturing method comprising: 
 in a semiconductor substrate having a first region and a second region, forming a first gate insulating film on the semiconductor substrate in the first region and forming a second gate insulating film on the semiconductor substrate in the second region;    forming a first gate wiring material on the first gate insulating film and the second gate insulating film;    forming a first element isolation insulating film by partially removing the first gate wiring material, the first gate insulating film, and the semiconductor substrate and forming a second element isolation insulating film by partially removing the first gate wiring material, the second gate insulating film, and the semiconductor substrate;    making a first height from an upper surface of the semiconductor substrate to an upper surface of the first element isolation insulating film smaller than a second height from the upper surface of the semiconductor substrate to an upper surface of the second element isolation insulating film by removing an upper portion of the first element isolation insulating film;    forming a second gate wiring material, third gate wiring material, and first mask layer sequentially in the first region and forming a fourth gate wiring material and a second mask layer sequentially in the second region; and    removing an upper portion of the first mask layer to make a height from the upper surface of the semiconductor substrate to an upper surface of the first mask layer equal to a height from the upper surface of the semiconductor substrate to an upper surface of the second mask layer.    
   
   
       14 . The method according to  claim 13 , wherein a second depth from the upper surface of the semiconductor substrate to a bottom surface of the second element isolation insulating film is larger than a first depth from the upper surface of the semiconductor substrate to a bottom surface of the first element isolation insulating film.  
   
   
       15 . The method according to  claim 13 , wherein in processing the first gate wiring material, the second gate wiring material, and the third gate wiring material in the first region, the upper portion of the first mask layer is removed.  
   
   
       16 . The method according to  claim 13 , further comprising forming a first contact above the first element isolation insulating film and forming a second contact above the second element isolation insulating film.  
   
   
       17 . The method according to  claim 13 , wherein 
 the first region is a memory cell region, and the second region is a peripheral circuit region, and    in the memory cell region, the first gate wiring material functions as a floating gate electrode, the second gate wiring material and the third gate wiring material function as a control gate electrode, and an insulating film is provided between the floating gate electrode and the control gate electrode.    
   
   
       18 . A semiconductor memory device manufacturing method comprising: 
 in a semiconductor substrate having a first region and a second region, forming a first gate insulating film on the semiconductor substrate in the first region and forming a second gate insulating film on the semiconductor substrate in the second region;    forming a first gate wiring material on the first gate insulating film and the second gate insulating film;    forming a first element isolation insulating film by partially removing the first gate wiring material, the first gate insulating film, and the semiconductor substrate and forming a second element isolation insulating film by partially removing the first gate wiring material, the second gate insulating film, and the semiconductor substrate;    making a first height from an upper surface of the semiconductor substrate to an upper surface of the first element isolation insulating film smaller than a second height from the upper surface of the semiconductor substrate to an upper surface of the second element isolation insulating film by removing an upper portion of the first element isolation insulating film;    forming a second gate wiring material in the first region, forming a third gate wiring material in the second region, and making upper surfaces of the second gate wiring material and the third gate wiring material flush with each other; and    forming a first mask layer on the second gate wiring material and forming a second mask layer on the third gate wiring material.    
   
   
       19 . The method according to  claim 18 , wherein a thickness of the second mask layer equals a thickness of the first mask layer.  
   
   
       20 . The method according to  claim 18 , wherein 
 the first region is a memory cell region, and the second region is a peripheral circuit region, and    in the memory cell region, the first gate wiring material functions as a floating gate electrode, the second gate wiring material functions as a control gate electrode, and an insulating film is provided between the floating gate electrode and the control gate electrode.