Thin film transistor array panel and manufacturing method thereof

Abstract

A method of manufacturing a thin film transistor array panel including forming a gate line on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming a data line and a drain electrode on the semiconductor layer, depositing a passivation layer on the data line and the drain electrode, forming a photoresist including a first portion and a second portion, which is thinner than the first portion, on the passivation layer, etching the passivation layer using the photoresist as a mask to expose a portion of the drain electrode, removing the second portion of the photoresist, depositing a conductive film, and removing the first portion of the photoresist to form a pixel electrode on the exposed portion of the drain electrode.

1 . A thin film transistor array panel, comprising: 
 a gate line formed on a substrate;    a gate insulating layer formed on the gate line;    a semiconductor layer formed on the gate insulating layer;    an ohmic contact formed on the semiconductor layer;    a data line and a drain electrode formed on the ohmic contact;    a passivation layer formed on the data line and the drain electrode and having a first contact hole exposing a portion of the drain electrode and a second contact hole exposing a portion of the date line;    a pixel electrode formed on the passivation layer and coupled with the drain electrode through the first contact hole; and    a first contact assistant formed on the exposed portion of the date line and having edges substantially coinciding with edges of the second contact hole.    
   
   
       2 . The thin film transistor array panel of  claim 1 , further comprising a second contact assistant, 
 wherein the gate insulating layer and the passivation layer have a third contact hole exposing a portion of the gate line, and    wherein the second contact assistant is formed on the exposed portion of the gate line and has edges substantially coinciding with edges of the third contact hole.    
   
   
       3 . The thin film transistor array panel of  claim 1 , wherein the semiconductor layer has substantially a same planar shape as the ohmic contact, the data line, and the drain electrode except for a portion of the semiconductor layer disposed in a channel region.