US2007105393A1PendingUtilityA1

Method for forming patterns and thin film transistors

46
Assignee: CHENG HSI-MINGPriority: Nov 4, 2005Filed: Nov 4, 2005Published: May 10, 2007
Est. expiryNov 4, 2025(expired)· nominal 20-yr term from priority
Inventors:Hsi-Ming Cheng
H10P 50/73H10P 14/412H10P 14/40H10W 20/081H10W 20/071H10W 20/031H10D 86/60H10D 86/40H10D 30/0321H10D 30/0314H10D 86/0231
46
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A method for forming a pattern is provided. First, a substrate is provided. Then, a discontinuous film is formed on the substrate so as to reduce the stress of the film. After that, the discontinuous film is patterned to form a pattern. Besides, a method for manufacturing a thin film transistor (TFT) is also provided. First, a substrate is provided. Then, a poly silicon island is formed on the substrate. After that, a gate insulating layer is formed to cover the poly silicon island. Then, a gate is formed on the gate insulating layer. After that, a source/drain is formed in the poly silicon island below one side and the other side of the gate respectively, and a channel layer is formed between the source/drain. At least one of the poly silicon island and the gate is formed according to the above mentioned method for forming the pattern.

Claims

exact text as granted — not AI-modified
1 . A method for forming a pattern, comprising: 
 providing a substrate;    forming a discontinuous film on the substrate to reduce the stress of the film; and    patterning the discontinuous film to form a pattern.    
   
   
       2 . The method for forming a pattern according to  claim 1 , wherein the discontinuous film is formed by a deposition process with a shadow mask.  
   
   
       3 . The method for forming a pattern according to  claim 1 , wherein the step of forming the discontinuous film on the substrate comprises; 
 forming a patterned bottom layer on the substrate; and    performing a deposition process to form the discontinuous film on the substrate.    
   
   
       4 . The method for forming a pattern according to  claim 3 , wherein the patterned bottom layer comprises a plurality of protrusive patterns or a plurality of concave patterns.  
   
   
       5 . The method for forming a pattern according to  claim 4 , wherein the top of the protrusive patterns is wider than the bottom thereof.  
   
   
       6 . The method for forming a pattern according to  claim 4 , wherein the top of the concave patterns is narrower than the bottom thereof.  
   
   
       7 . The method for forming a pattern according to  claim 1 , wherein the discontinuous film is patterned by a photolithography process and an etching process.  
   
   
       8 . A method for forming a thin film transistor, comprising: 
 providing a substrate;    forming a poly silicon island on the substrate;    forming a gate insulating layer to cover the poly silicon island;    forming a gate on the gate insulating layer; and    forming a source/drain in the poly silicon island below one side and the other side of the gate, wherein a channel layer is formed between the source/drain;    wherein at least one of the poly silicon island and the gate is formed by the method as recited in  claim 1 .    
   
   
       9 . The method for forming a thin film transistor according to  claim 8 , further comprising: 
 forming a patterned dielectric layer on the substrate, wherein the patterned dielectric layer exposes a part of the source/drain; and    forming a source/drain conducting layer on the patterned dielectric layer, wherein the source/drain conducting layer is electrically connected to the source/drain respectively;    wherein at least one of the patterned dielectric layer, the source/drain conducting layer is formed by the method as recited in  claim 1 .    
   
   
       10 . The method for forming a thin film transistor according to  claim 9 , wherein the step of forming the patterned dielectric layer comprises: 
 forming a dielectric layer on the substrate to cover the gate and the gate insulating layer;    forming a patterned photoresist layer having a first aperture and a second aperture on the dielectric layer;    performing a first etching process to remove the dielectric layer under the first aperture in order to form a concave pattern in the dielectric layer;    performing a second etching process to remove the dielectric layer and the gate insulating layer under the second aperture in order to expose the source/drain and remove the gate insulating layer under the first aperture simultaneously; and    removing the patterned photoresist layer.    
   
   
       11 . The method for forming a thin film transistor according to  claim 10 , wherein the method for forming the patterned photoresist layer comprises performing an exposure process by using a half-tone mask.  
   
   
       12 . The method for forming a thin film transistor according to  claim 10 , wherein before the second etching process is performed, the method further comprises an ashing process to make the second aperture expose the dielectric layer.  
   
   
       13 . The method for forming a thin film transistor according to  claim 10 , wherein before the poly silicon island is formed, the method further comprises a step of forming a buffer layer on the substrate, and the buffer layer is a discontinuous film.  
   
   
       14 . The method for forming a thin film transistor according to  claim 10 , wherein the gate insulating layer is a discontinuous film.  
   
   
       15 . The method for forming a thin film transistor according to  claim 10 , wherein the step of forming the poly silicon island comprises: 
 forming an amorphous silicon layer on the substrate, wherein the amorphous silicon layer is a discontinuous film;    performing an annealing process to make the amorphous silicon layer transform into a poly silicon layer; and    patterning the poly silicon layer to form the poly silicon island.    
   
   
       16 . A method for forming a thin film transistor, comprising: 
 forming a gate on a substrate;    forming a gate insulating layer on the substrate to cover the gate;    forming a channel layer on the gate insulating layer and the gate; and    forming a source/drain on the channel layer;    wherein at least one of the gate, the channel layer, the source/drain is formed by the method as recited in  claim 1 .    
   
   
       17 . The method for forming a thin film transistor according to  claim 16 , wherein before the source/drain is formed, the method further comprises the step of forming an ohmic contact layer on the channel layer, and the ohmic contact layer is formed by the method as recited in  claim 1 .  
   
   
       18 . The method for forming a thin film transistor according to  claim 16 , wherein the gate insulating layer is a discontinuous film.  
   
   
       19 . The method for forming a thin film transistor according to  claim 16 , wherein after the source/drain is formed, the method further comprises a step of forming a passivation layer to cover the source/drain, and the passivation layer is formed by the method as recited in  claim 1.

Cited by (0)

No later patents cite this yet.

References (0)

No backward citations on record.