US2007108610A1PendingUtilityA1

Embedded semiconductor device substrate and production method thereof

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Assignee: KONDO HIROSHIPriority: Nov 2, 2005Filed: Nov 2, 2006Published: May 17, 2007
Est. expiryNov 2, 2025(expired)· nominal 20-yr term from priority
Inventors:Hiroshi Kondo
H10W 70/682H10W 70/685H10W 70/099H10W 72/874H10W 72/877H10W 72/90H10W 72/9415H10W 72/00H10W 70/093H10W 70/60H10W 72/07331H10W 72/073H10W 72/354H10W 90/00H10W 72/20H10W 72/07251H10W 72/252H10W 90/736H10W 70/614H10P 72/7438H10P 72/74H10W 20/063
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Claims

Abstract

An embedded semiconductor device substrate having a semiconductor device integrated therein is formed by disposing a semiconductor device in an opening provided on an insulating resin, and sandwiching the semiconductor device and the insulating resin with a front surface wiring layer and a rear surface wiring layer and performing heat pressing. Connection between bumps of the semiconductor device and the front surface wiring layer is made with a connection wiring pattern. The connection wiring pattern is formed by patterning a resist film by direct exposure thereof with a light beam, and then performing etching. Thereby, it becomes possible to absorb a mounting error of a semiconductor device to a printed wiring board and a positional error of electrodes between semiconductor devices accompanying the tendency of reduction of the pitch of a semiconductor device, and to perform electric connection with a wiring pattern securely.

Claims

exact text as granted — not AI-modified
1 . An embedded semiconductor device substrate having a semiconductor device integrated in an insulating resin layer, wherein a wiring pattern is formed on the insulating resin layer, a bump for connection is formed on an electrode portion on the semiconductor device, and the wiring pattern and the bump are connected through a connection wiring pattern provided on the wiring pattern and the bump.  
     
     
         2 . The embedded semiconductor device substrate according to  claim 1 , wherein the connection wiring pattern is thinner than the wiring pattern.  
     
     
         3 . The embedded semiconductor device substrate according to  claim 1 , wherein the wiring has a multi-layer structure which is comprised of a plurality of materials.  
     
     
         4 . A method of producing an embedded semiconductor device substrate having a semiconductor device integrated therein, comprising the steps of: 
 forming a bump on an electrode portion on a surface of a semiconductor device;    disposing the semiconductor device in an opening formed on an substrate;    forming a conductive film on the semiconductor device and the substrate;    integrating the semiconductor device and the substrate into a single body;    patterning the conductive film to form wiring patterns and removing the conductive film on the semiconductor device to expose the bump; and    forming a connection wiring pattern for connecting the electrode portion on the semiconductor device and the wiring pattern.    
     
     
         5 . The method according to  claim 4 , wherein the connection wiring pattern is formed by forming a connection wiring layer on the substrate and the semiconductor device, patterning a resist material formed on the connection wiring layer by performing direct exposure with a laser, and then performing etching by using the resist material as an etching mask.  
     
     
         6 . The method according to  claim 4 , wherein the connection wiring pattern is formed by forming an under layer of a connection wiring layer on the substrate and the semiconductor device, patterning a resist material formed on the connection wiring layer by performing direct exposure with a laser, and then performing plating by using the resist material as a plating mask.  
     
     
         7 . The method according to  claim 4 , wherein the connection wiring pattern is formed by forming a connection wiring layer on the insulating resin layer and the semiconductor device, performing direct writing of a resist material on the connection wiring layer, and then performing etching.  
     
     
         8 . The method according to  claim 4 , wherein the connection wiring pattern is formed by performing direct writing of a conductive material on the insulating resin layer and the semiconductor device.

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