Buffered Thin Module System and Method

Abstract

Multiple fully buffered DIMM circuits or instantiations are presented in a single module. In a preferred embodiment, memory integrated circuits (preferably CSPs) and accompanying AMBs are arranged in two ranks in two fields on each side of a flexible circuit. The flexible circuit has expansion contacts disposed along one side. The flexible circuit is disposed about a supporting substrate or board to place one complete FB-DIMM circuit or instantiation on each side of the constructed module. In alternative but also preferred embodiments, the ICs on the side of the flexible circuit closest to the substrate are disposed, at least partially, in what are, in a preferred embodiment, windows, pockets, or cutaway areas in the substrate. Other embodiments may only populate one side of the flexible circuit or may only remove enough substrate material to reduce but not eliminate the entire substrate contribution to overall profile. The flexible circuit may exhibit one or two or more conductive layers, and may have changes in the layered structure or have split layers. Other embodiments may stagger or offset the ICs or include greater numbers of ICs.

1 . A circuit module comprising: 
 a first side and a second side, between which is disposed a substrate having a first perimeter edge and a second perimeter edge;    a plurality of module contacts comprising 
 a first row of contacts disposed along the first side of the circuit module proximal to the first perimeter edge of the substrate and  
 a second row of contacts disposed along the second side of the circuit module proximal to the first perimeter edge of the substrate;  
   a first FB-DIMM circuit comprising a first memory device and a first AMB, the first FB-DIMM circuit connected by first conductive traces to first selected ones of the plurality of module contacts; and    a second FB-DIMM circuit comprising a second memory device and a second AMB the second FB-DIMM circuit connected by second conductive traces to second selected ones of the plurality of module contacts.    
   
   
       2 . The circuit module of  claim 1  in which the first FB-DIMM circuit is disposed on the first side of the circuit module and the second FB-DIMM circuit is disposed on the second side of the circuit module  
   
   
       3 . The circuit module of  claim 1  in which the first FB-DIMM circuit is disposed proximal to the second perimeter edge of the substrate and the second FB-DIMM circuit is disposed proximal to the first perimeter edge of the substrate.  
   
   
       4 . The circuit module of  claim 1  in which the first memory device and the second memory device each comprises plural memory ICs.  
   
   
       5 . The circuit module of  claim 4  in which the plural memory ICs of the first memory device are arranged in a first field and the plural memory ICs of the second memory device are arranged in a second field.  
   
   
       6 . The circuit module of  claim 4  in which the plural memory ICs of the first memory device and the first AMB are disposed in a first FB-DIIMM row, and the plural memory ICs of the second memory device and the second AMB are disposed in a second FB-DIMM row.  
   
   
       7 . The circuit module of  claim 6  in which the first FB-DIMM row is disposed on the first side of the circuit module and the second FB-DIMM row is disposed on the second side of the circuit module.  
   
   
       8 . The circuit module of  claim 4  in which selected ones of the plural memory ICs of the first memory device are disposed on the first side of the circuit module and the first AMB is disposed on the second side of the circuit module.  
   
   
       9 . The circuit module of  claim 8  in which selected ones of the plural memory ICs of the second memory device are disposed on the second side of the circuit module and the second AMB is disposed on the first side of the circuit module.  
   
   
       10 . The circuit nodule of  claim 4  in which the plural memory ICs are deployed in stacks.  
   
   
       11 . The circuit module of  claim 10  in which the plural memory ICs are CSPs.  
   
   
       12 . The circuit module of  claim 11  in which each stack of CSPs comprises a mandrel.  
   
   
       13 . The circuit module of  claim 4  in which first selected ones of the plural memory ICs are disposed on the first side of the circuit module and second selected ones of the plural memory ICs are disposed on the second side of the circuit module, with each of the first selected ones of the plural memory ICs directly opposed to a respective one of the second selected ones of the plural memory ICs disposed on the opposite side of the substrate.  
   
   
       14 . The circuit module of  claim 4  in which first selected ones of the plural memory ICs are disposed on the first side of the circuit module and second selected ones of the plural memory ICs are disposed on the second side of the circuit module, with the first selected ones of the plural memory ICs offset from the second selected ones of the plural memory ICs disposed on the opposite side of the substrate.  
   
   
       15 . A memory module comprising plural FB-DIMM circuits.  
   
   
       16 . The memory module of  claim 15  in which each of the plural FB-DIMM circuits comprises plural memory CSPs.  
   
   
       17 . The memory module of  claim 16  in which selected ones of the plural memory CSPs are stacked.  
   
   
       18 . The memory module of  claim 17  in which selected ones of the stacked plural memory CSPs comprise a mandrel.  
   
   
       19 . The memory module of  claim 15  in which the first AMB is separated from the second AMB by a single impedance perturbation.  
   
   
       20 . A memory module comprising: 
 a support structure having first and second lateral sides and an edge;    a plurality of module contacts disposed adjacent to the edge of the support structure and supported by the first lateral side of the support structure;    a first FB-DIMM instantiation comprising a first memory device and a first AMB; and a second FB-DIMM instantiation comprising a second memory device and a second AMB.    
   
   
       21 . The memory module of  claim 20  in which the first memory device and the second memory device each comprises plural memory ICs.  
   
   
       22 . The memory module of  claim 21  in which the plural memory ICs of the first memory device and the first AMB are disposed in a first row, and the plural memory ICs of the second memory device and the second AMB are disposed in a second row.  
   
   
       23 . The memory module of  claim 22  in which the first row is disposed along the first side of the support structure and the second row is disposed along the second side of the support structure.  
   
   
       24 . The memory module of  claim 21  in which selected ones of the plural memory ICs of the first memory device are disposed along the first side of the support structure and the first AMB is disposed along the second side of the support structure.  
   
   
       25 . The memory module of  claim 24  in which selected ones of the plural memory ICs of the second memory device are disposed along the second side of the support structure and the second AMB is disposed along the first side of the support structure.  
   
   
       26 . The memory module of  claim 21  in which the first memory device and the second memory device each comprises stacks of memory ICs.  
   
   
       27 . The memory module of  claim 26  in which the memory ICs are CSPs.  
   
   
       28 . The memory module of  claim 27  in which each stack of CSPs comprises a mandrel.  
   
   
       29 . A circuit module comprising plural FD-DIMM instantiations.  
   
   
       30 . The memory module of  claim 29  in which each of the plural FB-DIMM instantiations comprises plural memory CSPs.  
   
   
       31 . The memory module of  claim 30  in which selected ones of the plural memory CSPs are stacked.  
   
   
       32 . The memory module of  claim 31  in which selected ones of the stacked plural memory CSPs comprise a mandrel.  
   
   
       33 . The memory module of  claim 29  in which the first AMB is separated from the second AMB by a single impedance perturbation.  
   
   
       34 . A computer comprising: 
 a motherboard having a socket and    a circuit module connected to the socket, the circuit module comprising plural FB-DIMM instantiations.