CPU life-extension apparatus and method

Abstract

A CPU life-extension apparatus and method makes a processor appear to be an upgraded CPU to substantially all software applications accessed thereby, thereby reducing the need and expense of upgrading a selected processor. A CPU life-extension module translates new instructions, intended for a CPU upgrade, into instructions recognized by the processor. In addition, the CPU life-extension module is programmed to monitor reads from and writes to a processor's flags register to modify the flags to emulate those of an upgraded CPU. The CPU life-extension module is configured to respond to interrupts generated by the processor in order to perform its various tasks.

1 . a method to extend the functionality of a processor to that of a subsequently: upgraded processor of the same processor family, the method comprising: 
 receiving, by the processor, a stream of instructions comprising a native instruction, recognized as such by the processor, and a new instruction, not so recognized;    processing the native instruction;    invoking a routine in response to the new instruction to handle it differently from the native instruction, wherein invoking comprises: 
 determining whether the new instruction is recognizable by the upgraded processor as native thereto;  
 providing, in the event the new instruction is recognizable by the upgraded processor, at least one native instruction in place of the new instruction to perform the function of the new instruction; and  
 generating a fault in the event the new instruction is not recognizable by the upgraded processor.  
   
     
     
         2 . The method of  claim 1 , further comprising monitoring READs and WRITEs to a flags register of the processor.  
     
     
         3 . The method of  claim 2 , further comprising modifying the READs and WRITEs to reflect values corresponding to the upgraded processor.  
     
     
         4 . The method of  claim 2 , wherein monitoring further comprises detecting when the processor pushes values onto a stack.  
     
     
         5 . The method of  claim 4 , wherein monitoring further comprises generating a stack-fault interrupt when an entry is pushed onto the stack.  
     
     
         6 . The method of  claim 5 , wherein monitoring further comprises invoking execution of a stack-fault handler in response to the stack-fault interrupt.  
     
     
         7 . The method of  claim 6 , wherein invoking execution of a stack-fault handler comprises detecting a pop operation due to be executed in the future.  
     
     
         8 . The method of  claim 7 , wherein invoking execution of a stack-fault handler comprises setting a breakpoint interrupt to occur in response to the pop operation.  
     
     
         9 . The method of  claim 8 , wherein invoking execution of a stack-fault handler comprises decrementing the stack size in response to the breakpoint interrupt.  
     
     
         10 . The method of  claim 1 , wherein the new instruction is selectively inserted into the stream of instructions at load time.  
     
     
         11 . An apparatus to extend the functionality of a processor to that of an upgraded processor of the same processor family, the apparatus comprising: 
 a processor configured to receive a stream of instructions comprising a native instruction, recognized as such by the processor, and new instruction, not so recognized by the processor;    the processor further configured to process the native instruction and generate an interrupt upon receiving the new instruction;    the processor further configured to invoke an interrupt service routine in response to the interrupt, wherein the interrupt service routine is configured to: 
 determine whether the new instruction is recognizable by the upgraded processor as native thereto;  
 provide, in the event the new instruction is recognizable by the upgraded processor, at least one native instruction in place of the new instruction to perform the function of the new instruction; and  
 generate a fault in the event the new instruction is not recognizable by the upgraded processor.  
   
     
     
         12 . The apparatus of  claim 11 , the processor further configured to monitor READs and WRITEs to a flags register of the processor.  
     
     
         13 . The apparatus of  claim 12 , the processor further configured to modify the READs and WRITEs to reflect values corresponding to the upgraded processor.  
     
     
         14 . The apparatus of  claim 12 , the processor further configured to detect when values are pushed onto a stack.  
     
     
         15 . The apparatus of  claim 14 , the processor further configured to generate a stack-fault interrupt when an entry is pushed onto the stack.  
     
     
         16 . The apparatus of  claim 15 , the processor further configured to invoke a stack-fault handler in response to the stack-fault interrupt.  
     
     
         17 . The apparatus of  claim 16 , wherein the stack-fault handler is configured to detect a pop operation due to be executed in the future.  
     
     
         18 . The apparatus of  claim 17 , wherein the stack-fault handler is configured to set a breakpoint interrupt to occur in response to the pop operation.  
     
     
         19 . The apparatus of  claim 18 , wherein the stack-fault handler is configured to decrement the stack size in response to the breakpoint interrupt.  
     
     
         20 . A method to extend the functionality of a processor to that of a subsequently upgraded processor of the same processor family, the method comprising: 
 receiving, by the processor, a stream of instructions comprising a native instruction, recognized as such by the processor, and a new instruction, not so recognized;    processing the native instruction;    generating an interrupt upon receiving the new instruction;    invoking an interrupt service routine in response to the interrupt, wherein invoking comprises: 
 determining whether the new instruction is recognizable by the upgraded processor as native thereto;  
 providing, in the event the new instruction is recognizable by the upgraded processor, at least one native instruction in place of the new instruction to perform the function of the new instruction; and  
 generating a fault in the event the new instruction is not recognizable by the upgraded processor.