Non-volatile memory

Abstract

A NVM including a substrate, a control gate layer, a charge storage layer, a tunneling layer, a charge barrier layer, a gate dielectric layer and a first doping region is described. The control gate layer is disposed in a first trench of the substrate; the charge storage layer is disposed between the sidewall of the first trench and the control gate layer; the tunneling layer is disposed between the sidewall of the first trench and the charge storage layer; the charge barrier layer is disposed between the charge storage layer and the control gate layer; the gate dielectric layer is disposed between the bottom of the first trench and the control gate layer; and the first doping region is disposed in the substrate at one side of the control gate layer.

1 . A non-volatile memory (NVM), comprising: 
 a control gate layer, disposed in a first trench of a substrate;    a charge storage layer, disposed between a sidewall of the first trench and the control gate layer;    a charge tunneling layer, disposed between the sidewall of the first trench and the charge storage layer;    a charge barrier layer, disposed between the charge storage layer and the control gate layer;    a gate dielectric layer, disposed between the bottom of the first trench and the control gate layer; and    a first doping region, disposed in the substrate at one side of the control gate layer.    
   
   
       2 . The non-volatile memory as recited in  claim 1 , further comprising a second doping region disposed at the bottom of the first trench.  
   
   
       3 . The non-volatile memory as recited in  claim 2 , further comprising an isolation spacer disposed between the charge barrier layer on the sidewall of the first trench and the control gate layer.  
   
   
       4 . The non-volatile memory as recited in  claim 1 , further comprising an isolation layer disposed in a second trench of the substrate, wherein the first trench crosses over the second trench.  
   
   
       5 . The non-volatile memory as recited in  claim 4 , wherein a depth of the second trench is larger than that of the first trench.  
   
   
       6 . The non-volatile memory as recited in  claim 1 , further comprising: 
 a plurality of first trenches in the substrate, wherein the first trench is one of the first trenches;    a plurality of second trenches in the substrate, wherein the second trenches are located under the first trenches and cross the first trenches;    a plurality of isolation layers, filled into the second trenches;    a plurality of control gate layers, filled into the first trenches and crossing over the isolation layers, wherein the control gate layer is one of the control gate layers;    a plurality of charge storage layers, disposed between sidewalls of the first trenches and the control gate layers, wherein the charge storage layer is one of the charge storage layers;    a plurality of charge tunneling layers, disposed between sidewalls of the first trenches and the charge storage layers, wherein the charge tunneling layer is one of the tunneling layers;    a plurality of charge barrier layers, disposed between the charge storage layers and the control gate layers, wherein the charge barrier layer is one of the charge barrier layers;    a plurality of gate dielectric layers, disposed between bottoms of the first trenches and the control gate layers, wherein the gate dielectric layer is one of the gate dielectric layers; and    a plurality of first doping regions, disposed in the substrate at both sides of the control gate layers, wherein the first doping region is one of the first doping regions.    
   
   
       7 . The non-volatile memory as recited in  claim 6 , further comprising a plurality of second doping regions disposed at bottoms of the first trenches and located in the substrate between two adjacent second trenches.  
   
   
       8 . The non-volatile memory as recited in  claim 7 , further comprising a pair of isolation spacers, disposed between each charge barrier layer on both sidewalls of each first trench and each control gate layer, respectively.  
   
   
       9 . The non-volatile memory as recited in  claim 8 , wherein depths of the second trenches are larger than those of the first trenches.  
   
   
       10 . The non-volatile memory as recited in  claim 6 , wherein two tunneling layers, two charge storage layers and two charge barrier layers are disposed sequentially on both sidewalls of the control gate, respectively.