Method of fabricating flash memory

Abstract

A method for fabricating a flash memory is described. A mask layer having openings to expose a portion of the substrate is formed on the substrate. A tunneling dielectric layer is formed at the bottom surface of the openings. Conductive spacers are formed on the sidewalls of the openings. The conductive spacers are patterned to form a plurality of floating gates. A plurality of buried doped regions is formed in the substrate under the bottom surface of the openings. An inter-gate dielectric layer is formed over the substrate. A plurality of control gates is formed over the substrate to fill the openings. The mask layer is removed to form a plurality of memory units. A plurality of source regions and drain regions are formed in the substrate beside the memory units.

1 . A method for fabricating a flash memory device, comprising: 
 providing a substrate;    forming a mask layer over the substrate, wherein the mask layer comprises a plurality of openings that expose a part of the substrate;    forming a tunneling dielectric layer at a bottom of each opening;    forming a plurality of stripe-shaped conductive spacers on sidewalls of the openings;    patterning the stripe-shaped conductive spacers to form a plurality of floating gates;    forming a plurality of buried doped regions in the substrate at the bottoms of the openings using the floating gates as a mask;    forming an inter-gate dielectric layer over the substrate;    forming a plurality of control gates over the substrate to fill the openings;    forming a plurality of memory units after the mask layer is removed; and    forming a plurality of source regions and a plurality of drain regions in the substrate beside the memory units.    
   
   
       2 . The method of  claim 1 , wherein the step of forming the plurality of the stripe-shaped conductive spacers on the sidewalls of the openings further comprises: 
 forming a first conductive layer over the substrate; and    removing a portion of the first conductive layer using a self-aligned etching process to form the stripe-shaped conductive spacers on the sidewalls of the openings.    
   
   
       3 . The method of  claim 1 , wherein the step of forming the plurality of the control gates over the substrate to fill the openings further comprises: 
 forming a second conductive layer over the substrate; and    removing a portion of the second conductive layer outside the openings to form the control gates.    
   
   
       4 . The method of  claim 3 , wherein the step of removing the portion of the second conductive layer outside the openings comprises performing an etching process or a chemical mechanical polishing process.  
   
   
       5 . The method of  claim 1 , wherein a material used in forming the mask layer has an etching selectivity different from those of the floating gate and the control gate.  
   
   
       6 . The method of  claim 1 , wherein a material used in constituting the mask layer comprises silicon nitride.  
   
   
       7 . The method of  claim 1 , wherein after the step of forming the source regions and the drain regions, the method further comprises: 
 forming a dielectric layer over the substrate; and    forming a plurality of source region contacts and a plurality of drain region contacts in the dielectric layer.    
   
   
       8 . The method of  claim 1 , wherein a material constituting the inter-gate dielectric layer comprises silicon oxide/silicon nitride/silicon oxide.  
   
   
       9 . The method of  claim 1 , wherein a material constituting the inter-gate dielectric layer comprises silicon oxide.  
   
   
       10 . The method of  claim 1 , wherein a material constituting the control gates and the floating gates comprises doped polysilicon.  
   
   
       11 . The method of  claim 1 , wherein the substrate is doped with dopants of a first conductive type and the source regions, the drain regions and the buried doped regions are doped with dopants of a second conductive type.  
   
   
       12 . The method of  claim 11 , wherein the substrate further comprises a deep doped region of the second conductive type and a shallow doped region of the first conductive type, wherein the shallow doped region is formed in the deep doped region, and the source regions, the drain regions and the buried doped regions are formed in the shallow doped region.