A content addressable memory including capacitor memory cell

Abstract

A content addressable memory is realized, wherein capacitor stores data and diode controls to store data “1” or “0”, which diode has four terminals, first terminal serves as word line, second terminal serves as storage node, third terminal is floating, and fourth terminal serves as bit line. The plate of capacitor couples to second terminal, but it does not couple to first, third and fourth terminal. With no coupling, the plate can swing ground to high level, which can realize to remove internal negative voltage for memory operation and by turning off word line during standby no holding current is required to sustain data. In this manner, active current is dramatically reduced and standby current is only leakage current. The match line has compare circuits which include series MOS transistors for each memory cell, wherein the storage node is connected to the gate of first MOS transistor, and the comparand data is connected to the gate of second MOS transistor. Hidden refresh is asserted during precharge of match operation. The size of CAM is smaller than that of SRAM, DRAM-based CAM, and the height of cell is almost same as that of control circuit.

1 . A content addressable memory, comprising: 
 capacitor memory cell wherein includes a capacitor and a diode, which capacitor stores data and diode controls to store data “1” or “0”, which diode has four terminals, first terminal is n-type and serves as word line, second terminal is p-type and serves as storage node, third terminal is n-type and floating, fourth terminal is p-type and serves as bit line, and plate of capacitor couples to second terminal, which plate has no coupling region to first, third and fourth terminal; and    at least one compare circuit coupled among the memory cell and at least one match line to receive first and second signal sets and affect a logical state of the match line in response to a predetermined logical relationship between the first and second signal sets, the compare circuit including a first transistor set and a second transistor set, wherein the first signal set couples to control a conduction state of the first transistor set and the second signal set couples to control a conduction state of the second transistor set, wherein the first signal set includes stored data and the second signal set includes comparand data.    
   
   
       2 . The content addressable memory of  claim 1 , wherein can be implemented an alternative embodiment with reverse configuration, such that diode has four terminals, wherein first terminal is p-type and serves as word line, second terminal is n-type and serves as storage node, third terminal is p-type and floating, fourth terminal is n-type and serves as bit line, and plate of capacitor couples second terminal, which plate has no coupling region to first, third and fourth terminal.  
   
   
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       12 . The content addressable memory of  claim 1 , wherein the capacitor has higher dielectric constant than that of control circuit in the chip.  
   
   
       13 . The content addressable memory of  claim 1 , wherein the diode is formed from silicon diode.  
   
   
       14 . The content addressable memory of  claim 1 , wherein the fourth terminal of the diode uses metal to form metal semiconductor diode.  
   
   
       15 . The content addressable memory of  claim 1 , wherein the diode is formed from compound semiconductor diode, such as GaAs, SiGe.  
   
   
       16 . The content addressable memory of  claim 1 , wherein the diode is formed from germanium diode.  
   
   
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