Phase change memory including diode access device

Abstract

Phase change memory including diode access device is realized, wherein includes a chalcogenide storage element and a diode access device instead of MOS device, the diode has four terminals, the first terminal is connected to a word line, the second terminal is connected to one side of the storage element, the third terminal is floating, the fourth terminal is connected to a bit line, and the other side of the storage element is connected to a resistor line which has floating state just before the word line is asserted to establish the current path of the memory cell. Replica delay circuit controls the read path, which minimizes the read current pulse, induces less current disturbance to the stored data, makes the read access time fast and reduces the current consumption. And the word line cuts off the holding current during standby. Additionally, planar and vertical cell structures are devised on the bulk and SOI wafer.

1 . A random access memory, comprising: 
 memory cell, wherein includes a resistive storage element and a diode; and    the resistive storage element includes phase change material as a storage element, wherein includes two electrodes, one electrode serves as a storage node and another electrode is connected to a resistor line; and    the diode as an access device, wherein includes four terminals, the first terminal is p-type and connected to a word line, the second terminal is n-type and connected to the storage node of the resistive storage element, the third terminal is p-type and floating, the fourth terminal is n-type and connected to a bit line; and    read circuits, wherein includes a MOS transistor, a current mirror and a data latch; drain and gate of the MOS transistor are connected to the bit line through the read switch, in order to sink the current from the diode when the word line is asserted; and the current mirror is connected to the gate of the MOS transistor, which mirror repeats the current that the diode sinks, and a latch node of the data latch is connected to the current mirror, thus the latch node is changed by the current mirror from the pre-charged state, after the word line and the resistor line are asserted to measure the resistance value of the resistive storage element, when the resistive storage element stores high resistance, which does not affect the current path of the diode with less current flow through the storage element; otherwise, when the resistive storage element stores low resistance, which affects the current path of the diode with high current flow through the storage element, thus the storage node is pulled up by the current of the storage element, and which cuts off the current path of the diode, as a result the current mirror does not flow current, and the latch node is not changed by the current mirror, when the read switch is turned on.    
     
     
         2 . The random access memory of  claim 1 , wherein the diode includes four terminals, the first terminal is n-type, the second terminal is p-type, the third terminal is n-type, and the fourth terminal is p-type.  
     
     
         3 . The random access memory of the  claim 1 , wherein the current mirror includes low threshold NMOS transistor.  
     
     
         4 . The random access memory of  claim 1 , wherein the swing level of resistor line is from the first predetermined positive level to the second predetermined positive level.  
     
     
         5 . The random access memory of  claim 1 , wherein the diode is formed from silicon, germanium, or compound semiconductor.  
     
     
         6 . The random access memory of  claim 1 , wherein the diode is formed from metal-semiconductor diode (Schottky diode).  
     
     
         7 . The random access memory of  claim 1 , wherein the diode is laterally formed.  
     
     
         8 . The random access memory of  claim 1 , wherein at least one of four terminals of the diode is vertically attached to adjacent terminal.  
     
     
         9 . The random access memory of  claim 1 , wherein the resistive storage elements is are arrayed in vertically zigzagged shape, in order to increase the effective distance from the adjacent storage elements.  
     
     
         10 . The random access memory of  claim 1 , wherein is formed on the isolation layer of the wafer.