US2007133256A1PendingUtilityA1

Integrated circuit with a memory of reduced consumption

Assignee: BONZO ANDREAPriority: Dec 13, 2004Filed: Feb 1, 2007Published: Jun 14, 2007
Est. expiryDec 13, 2024(expired)· nominal 20-yr term from priority
G11C 11/417
24
PatentIndex Score
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Claims

Abstract

An integrated circuit -comprising volatile memory elements, interface circuits connected to the volatile memory elements and, possibly, logic circuits not connected to the volatile memory elements and comprising first, second, and possibly third separate power supplies, the first power supply being connected to the volatile memory elements, the second power supply being connected to the interface circuits with the memory elements, and the third power supply being connected to other logic circuits.

Claims

exact text as granted — not AI-modified
1 - 10 . (canceled)  
   
   
       11 . An integrated circuit comprising: 
 volatile memory elements,    logic interface circuits connected to the volatile memory elements,    first and second separate power supplies, the first power supply being connected to the volatile memory elements and the second power supply being connected to the logic interface circuits, and    additional logic circuits, and a third power supply, separate from the first and second power supplies, connected to the additional logic circuits,    wherein, the volatile memory elements comprise MOS transistors of a first type, the logic interface circuits comprise MOS transistors of a second type different from the first type, and the additional logic circuits comprise MOS transistors of a third type different from the first type and the second type.    
   
   
       12 . The integrated circuit of  claim 11 , wherein the transistors of the first type have leakage currents smaller than the transistors of the second type.  
   
   
       13 . The integrated circuit of  claim 12 , wherein the transistors of the first type have leakage currents smaller than the transistors of the third type.  
   
   
       14 . The integrated circuit of  claim 11 , wherein the first, second, and third power supplies are set to different levels in a first operating mode.  
   
   
       15 . The integrated circuit of  claim 11 , wherein the second and third power supplies are turned off and the first power supply is set to a non-zero level in a first operating mode.  
   
   
       16 . The integrated circuit of  claim 12 , wherein the transistors of the third type having a switching rate greater than the switching rate of the transistors of the second type.

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