Full depletion SOI-MOS transistor

Abstract

A method of manufacturing a full depletion SOI-MOS transistor including a substrate, a buried oxide layer, a thin silicon layer, an isolation layer, a gate insulation layer, a gate electrode and a polysilicon layer. The buried oxide layer is formed on a main surface of the substrate. The thin silicon layer is formed on the buried oxide layer and includes a channel region and a source/drain region. The isolation layer is formed on the buried oxide layer and surrounds the thin silicon layer. A gate insulation layer and gate electrode are formed on the channel region of the thin silicon layer. The polysilicon layer is deposited on the source/drain region of the thin silicon layer.

1 . A method of manufacturing a full depletion SOI-MOS transistor comprising: 
 providing a substrate having a main surface;    forming a buried oxide layer on the main surface of the substrate;    forming a thin silicon layer on the buried oxide layer, the thin silicon layer including impurity activated source/drain regions and a channel region between the impurity activated source/drain regions;    forming an isolation layer on the buried oxide layer, the isolation layer being disposed adjacent the thin silicon layer;    forming a gate insulation layer on the channel region of the thin silicon layer;    forming a gate electrode on the gate insulation layer; and    depositing a polysilicon layer on the impurity activated source/drain regions of the thin silicon layer and on top of the isolation layer,    the impurity activated source/drain regions and the deposited polysilicon layer together respectively forming a source and a drain of the full depletion SOI-MOS transistor.    
     
     
         2 . The method of manufacturing a full depletion SOI-MOS transistor according to  claim 1 , further comprising a forming sidewall on the gate insulation layer, adjacent the gate electrode.  
     
     
         3 . The method of manufacturing a full depletion SOI-MOS transistor according to  claim 2 , wherein the polysilicon layer extends on the sidewall.  
     
     
         4 . The method of manufacturing a full depletion SOI-MOS transistor according to  claim 1 , wherein a thickness of the thin silicon layer is about 20 to 80 percent of a total thickness of the thin silicon layer and the polysilicon layer.  
     
     
         5 . The method of manufacturing a full depletion SOI-MOS transistor according to  claim 1 , wherein a thickness of the thin silicon layer is less than about 35 nm.  
     
     
         6 . A method of manufacturing a full depletion SOI-MOS transistor comprising: 
 providing a substrate having a main surface;    forming a BOX layer on the main surface of the substrate;    forming an SOI layer on the BOX layer, the SOI layer including impurity activated source/drain regions and a channel region between the impurity activated source/drain regions;    forming an isolation layer on the BOX layer, the isolation layer being disposed adjacent the SOI layer;    forming a gate insulation layer on the channel region of the SOI layer;    forming a gate electrode on the gate insulation layer; and    depositing a high mobility conductive layer on the impurity activated source/drain regions of the thin silicon layer and on top of the isolation layer,    the deposited high mobility conductive layer containing polysilicon, the impurity activated source/drain regions and the deposited high mobility conductive layer together respectively forming a source and a drain of the full depletion SOI-MOS transistor.    
     
     
         7 . The method of manufacturing a full depletion SOI-MOS transistor according to  claim 6 , further comprising forming a sidewall on the gate insulation layer, adjacent the gate electrode.  
     
     
         8 . The method of manufacturing a full depletion SOI-MOS transistor according to  claim 7 , wherein the high mobility conductive layer extends on the sidewall.  
     
     
         9 . The method of manufacturing a full depletion SOI-MOS transistor according to  claim 6 , wherein a thickness of the SOI layer is about 20 to 80 percent of a total thickness of the SOI layer and the high mobility conductive layer.  
     
     
         10 . The method of manufacturing a full depletion SOI-MOS transistor according to  claim 6 , wherein a thickness of the SOI layer is less than about 35 nm.  
     
     
         11 . The method of manufacturing a full depletion SOI-MOS transistor according to  claim 6 , wherein the high mobility conductive layer contains silicide.  
     
     
         12 . The method of manufacturing a full depletion SOI-MOS transistor according to  claim 6 , further comprising depositing the high mobility conductive layer on the gate electrode.