Semiconductor device and manufacturing method of the same

Abstract

A semiconductor device which combines reliability and the guarantee of electrical characteristics is provided. A power MOSFET and a protection circuit formed over the same semiconductor substrate are provided. The power MOSFET is a trench gate vertical type P-channel MOSFET and the conduction type of the gate electrode is assumed to be P-type. The protection circuit includes a planar gate horizontal type offset P-channel MOSFET and the conduction type of the gate electrode is assumed to be N-type. These gate electrode and gate electrode are formed in separate steps.

1 . A semiconductor device comprising; 
 a P-channel trench gate MOSFET formed over a main face of a semiconductor substrate,    wherein a P-channel planar gate MOSFET is formed over the same main face of the semiconductor substrate as the trench gate MOSFET.    
     
     
         2 . The semiconductor device according to  claim 1 , 
 wherein the conduction type of the gate electrode of the trench gate MOSFET is P-type, and    wherein the conduction type of the gate electrode of the planar gate MOSFET is N-type.    
     
     
         3 . The semiconductor device according to  claim 1 , 
 wherein the trench gate MOSFET is a power MOSFET, and    wherein the planer gate MOSFET includes a protection circuit which protects the trench gate MOSFET.    
     
     
         4 . The semiconductor device according to  claim 3 , 
 wherein the planer gate MOSFET has an offset drain structure.    
     
     
         5 . The semiconductor device according to  claim 3 , 
 wherein the protection circuit is a temperature detection overheat cutoff circuit.    
     
     
         6 . The semiconductor device according to  claim 3 , 
 wherein the protection circuit is an over-current limit circuit.    
     
     
         7 . A manufacturing method of a semiconductor device in which a P-channel trench gate MOSFET and a P-channel planer gate MOSFET are formed over the same main face of a semiconductor substrate, 
 wherein a gate of the trench gate MOSFET and a gate of the planer gate MOSFET are formed in separate steps.    
     
     
         8 . The manufacturing method of a semiconductor device according to  claim 7 , 
 wherein the conduction type of the gate electrode of the trench gate MOSFET is P-type, and    wherein the conduction type of the gate electrode of the planar gate MOSFET is N-type.    
     
     
         9 . The manufacturing method of a semiconductor device according to  claim 7 , 
 wherein the trench gate MOSFET is a power MOSFET, and    wherein the planer gate MOSFET includes a protection circuit which protects the trench gate MOSFET.    
     
     
         10 . The manufacturing method of a semiconductor device according to  claim 9 , 
 wherein the planer gate MOSFET has an offset drain structure.    
     
     
         11 . The manufacturing method of a semiconductor device according to  claim 9 , 
 wherein the protection circuit is a temperature detection overheat cutoff circuit.    
     
     
         12 . The manufacturing method of a semiconductor device according to  claim 9 , 
 wherein the protection circuit is an over-current limit circuit.    
     
     
         13 . A manufacturing method of a semiconductor device in which a P-channel trench gate MOSFET and a P-channel planer gate MOSFET are formed over the same main face of a semiconductor substrate comprising the steps of: 
 (a) preparing the semiconductor substrate;    (b) forming a trench groove in a first region of the main face of the semiconductor substrate;    (c) forming a first gate insulator film over the side wall in the trench groove;    (d) forming a first gate electrode over the first gate insulator film so as to be buried inside the trench groove;    (e) forming a second gate insulator film in a second region of the main face of the semiconductor substrate; and    (f) forming a second gate electrode over the second gate insulator film,    wherein the step (d) and the step (f) are separate steps.    
     
     
         14 . The manufacturing method of a semiconductor device according to  claim 13 , 
 wherein the step (d) comprises the steps of:    (d1) forming a silicon film over the main face of the semiconductor substrate;    (d2) introducing an impurity to make the silicon film a P-type conduction type; and    (d3) removing a part of the silicon film and forming the first gate electrode.    
     
     
         15 . The manufacturing method of a semiconductor device according to  claim 14 , 
 wherein the impurity is boron.    
     
     
         16 . The manufacturing method of a semiconductor device according to  claim 13 , 
 wherein the step (f) comprises the steps of:    (f1) forming a silicon film over the main face of the semiconductor substrate;    (f2) introducing an impurity to make the silicon film an N-type conduction type; and    (f3) removing a part of the silicon film and forming the second gate electrode.    
     
     
         17 . The manufacturing method of a semiconductor device according to  claim 16 , 
 wherein the impurity is arsenic.    
     
     
         18 . The manufacturing method of a semiconductor device according to  claim 13 , 
 wherein the step (f) comprises the steps of:    (f1) forming a silicon film having an N-type conduction type over the main face of the semiconductor substrate; and    (f2) removing a part of the silicon film and forming the second gate electrode.    
     
     
         19 . The manufacturing method of a semiconductor device according to  claim 13 , 
 wherein a drain of the planer gate MOSFET includes a first semiconductor region and a second semiconductor region formed over the main face of the semiconductor substrate,    wherein the impurity concentration of the first semiconductor region is lower than the impurity concentration of the second semiconductor region, and    wherein the first semiconductor region is formed between the second gate electrode and the second semiconductor region.    
     
     
         20 . The manufacturing method of a semiconductor device according to  claim 13 , 
 wherein the step (f) is carried out after the step (d).    
     
     
         21 . The manufacturing method of a semiconductor device according to  claim 20 , 
 wherein an insulator film is formed so as to cover the first gate between the step (d) and the step (f).