Semiconductor device and method for manufacturing the same

Abstract

Gate length is 110 nm±15 nm or shorter (130 nm or shorter in a design rule) or an aspect ratio of an area between adjacent gate electrode structures thereof (ratio of the height of the gate electrode structure to the distance between the gate electrode structures) is 6 or higher. A PSG (HDP-PSG: Phospho Silicate Glass) film containing a conductive impurity is formed as an interlayer insulating film for burying the gate electrode structures at film-formation temperature of 650° C. or lower by a high-density plasma CVD (HDP-CVD) method.

1 . A method for manufacturing a semiconductor device comprising the steps of: 
 forming a plurality of gate electrode structures on a semiconductor substrate with a gate insulating film therebetween so that an aspect ratio of a part between adjacent gate electrode structures is 6 or higher; and    forming a silicon oxide film containing a conductive impurity at film-formation temperature of 650° C. or lower by a high-density plasma CVD method in a manner of filling said part between said adjacent gate electrode structures and burying said gate electrode structures.    
     
     
         2 . The method for manufacturing the semiconductor device according to  claim 1 , 
 wherein said silicon oxide film is a PSG film.    
     
     
         3 . The method for manufacturing the semiconductor device according to  claim 1 , 
 wherein said gate electrode structures are formed in a manner in which pattern-formed gate electrodes are covered with an insulating film, and said silicon oxide film is formed in a manner of burying said gate electrode structures.    
     
     
         4 . The method for manufacturing the semiconductor device according to  claim 2 , 
 wherein said gate electrode structures are formed in a manner in which pattern-formed gate electrodes are covered with an insulating film, and said silicon oxide film is formed in a manner of burying said gate electrode structures.    
     
     
         5 . The method for manufacturing the semiconductor device according to  claim 1 , 
 wherein, in forming said silicon oxide film, a growth gas containing He gas is used.    
     
     
         6 . The method for manufacturing the semiconductor device according to  claim 2 , 
 wherein, in forming said silicon oxide film, a growth gas containing He gas is used.    
     
     
         7 . The method for manufacturing the semiconductor device according to  claim 3 , 
 wherein, in forming said silicon oxide film, a growth gas containing He gas is used.    
     
     
         8 . The method for manufacturing the semiconductor device according to  claim 4 , 
 wherein, in forming said silicon oxide film, a growth gas containing He gas is used.    
     
     
         9 . The method for manufacturing the semiconductor device according to  claim 1 , 
 wherein, the step of forming said silicon oxide film comprises the step of letting He gas flow toward a rear face of said semiconductor substrate, thereby controlling said film-formation temperature.    
     
     
         10 . The method for manufacturing the semiconductor device according to  claim 1 , 
 wherein, in forming said silicon oxide film, film-formation pressure is set at 0.47 Pa or lower.    
     
     
         11 . A semiconductor device comprising: 
 at least one gate electrode structure formed on a semiconductor substrate with a gate insulating film therebetween and having gate length of  110  nm or shorter; and    a silicon oxide film containing a conductive impurity formed by a high-density plasma CVD method so that difference in a surface level due to said gate electrode structure is lessened.    
     
     
         12 . The semiconductor device according to  claim 11 , 
 wherein said silicon oxide film is a PSG film.    
     
     
         13 . The semiconductor device according to  claim 11 , 
 wherein said gate electrode structure comprises a gate electrode, and an insulating film which covers said gate electrode.    
     
     
         14 . The semiconductor device according to  claim 12 , 
 wherein said gate electrode structure comprises a gate electrode, and an insulating film which covers said gate electrode.    
     
     
         15 . The semiconductor device according to  claim 11 , 
 wherein an aspect ratio of a part between adjacent gate electrode structures is 6 or higher.    
     
     
         16 . The semiconductor device according to  claim 12 , 
 wherein an aspect ratio of a part between adjacent gate electrode structures is 6 or higher.    
     
     
         17 . The semiconductor device according to  claim 13 , 
 wherein an aspect ratio of a part between adjacent gate electrode structures is 6 or higher.    
     
     
         18 . The semiconductor device according to  claim 14 , 
 wherein an aspect ratio of a part between adjacent gate electrode structures is 6 or higher.    
     
     
         19 . A semiconductor device comprising: 
 a plurality of gate electrode structures formed on a semiconductor substrate with a gate insulating film therebetween so that an aspect ratio of a part between adjacent gate electrode structures is 6 or higher; and    a silicon oxide film containing a conductive impurity formed by a high-density plasma CVD method in a manner of filling the part between said adjacent gate electrode structures and burying said gate electrode structures.    
     
     
         20 . The semiconductor device according to  claim 19 , 
 wherein said silicon oxide film is a PSG film.    
     
     
         21 . The semiconductor device according to  claim 19 , 
 wherein said gate electrode structures are formed in a manner in which gate electrodes are covered with an insulating film.    
     
     
         22 . The semiconductor device according to  claim 20 , 
 wherein said gate electrode structures are formed in a manner in which gate electrodes are covered with an insulating film.