Stack type surface acoustic wave package, and method for manufacturing the same

Abstract

Disclosed herein is a stack type surface acoustic wave package. The surface acoustic wave package comprises a first bare chip having a plurality of electrodes formed thereon, a second bare chip having a plurality of electrodes and via-holes formed thereon, a connecting portion electrically connecting the first bare chip to an upper surface of the second bare chip such that the electrodes of the first bare chip face the electrodes of the second bare chip, and a sealing member provided on the first and second bare chips to form an air-tight space on an operating surface between the first and second bare chips. The surface acoustic wave package can prevent deformation due to thermal impact from the outside during a packaging process, enhancing reliability of the product, minimizing the size of the product, and reducing manufacturing costs by reducing the number of components and material costs.

1 . A method for manufacturing a stack type surface acoustic wave package, comprising the steps of: 
 a) preparing a lower wafer having input, output and IDT electrodes formed on an upper surface thereof, and a plurality of via-holes passing through the lower wafer;    b) bonding first bare chips, each having input, output and IDT electrodes formed thereon, to the lower wafer via a metallic bonding agent;    c) laminating a resin film on the lower wafer to cover side and upper surfaces of the first bare chips;    d) removing the resin film to a predetermined depth along a boundary between the first bare chips to form separating grooves therebetween;    e) plating a metal layer of a predetermined thickness on the resin film and the separating grooves; and    f) cutting a central portion between the separating grooves plated with the metal layer.    
   
   
       2 . The method according to  claim 1 , wherein the step a) comprises printing a conductive pattern on upper ends of the via-holes to be electrically connected to the input and output electrodes, and another conductive pattern on lower ends of the via-holes to be electrically connected to a main board.  
   
   
       3 . The method according to  claim 1 , wherein the step b) comprises flip-chip bonding of the first bare chips to the lower wafer via the metallic bonding agent such that the input and output electrodes, and the IDT electrodes of each first bare chip face the input and output electrodes, and the IDT electrodes of the lower wafer, respectively.  
   
   
       4 . The method according to  claim 3 , wherein flip-chip bonding of the first bare chips to the lower wafer comprises supersonic bonding by use of stud bumps interposed between a conductive pad laid on the input and output electrodes of each first bare chip and a conductive pattern of the input and output electrodes of the lower wafer.  
   
   
       5 . The method according to  claim 3 , wherein flip-chip bonding of the first bare chips to the lower wafer comprises thermal bonding by use of AuSn-based solder bumps interposed between a conductive pad laid on the input and output electrodes of each first bare chip and a conductive pattern of the input and output electrodes of the lower wafer.  
   
   
       6 . The method according to  claim 1 , wherein the step c) comprises laminating the resin film formed of a thermosetting material by thermal compression.  
   
   
       7 . The method according to  claim 6 , wherein the thermosetting resin film is one selected from a polyimide based film and an epoxy-based film.  
   
   
       8 . The method according to  claim 1 , wherein, at the step d), the separating grooves are formed to an extent that the upper surface of the lower wafer is exposed to the outside.  
   
   
       9 . The method according to  claim 1 , wherein, at the step e), the metal layer is electrically connected to an inner ground terminal to prevent electromagnetic waves from being induced from the outside.  
   
   
       10 . The method according to  claim 1 , wherein, at the step e), the metal layer is plated by an electroplating process.  
   
   
       11 . A method for manufacturing a stack type surface acoustic wave package, comprising the steps of: 
 a) preparing a lower wafer having input, output and IDT electrodes formed on an upper surface thereof, and a plurality of via-holes passing through the lower wafer;    b) forming a metal dam to surround the input, output and IDT electrodes of the lower wafer;    c) bonding an upper wafer having input, output and IDT electrodes formed thereon onto the lower wafer via a metallic bonding agent;    d) forming separating grooves spaced a predetermined from each other and having a predetermined depth on the upper wafer;    e) plating a metal layer of a predetermined thickness from the upper surface of the metal dam to cover the upper wafer; and    f) dicing a central portion between the separating grooves plated with the metal layer.    
   
   
       12 . The method according to  claim 11 , wherein the step a) comprises printing a conductive pattern on upper ends of the via-holes to be electrically connected to the input and output electrodes, and another conductive pattern on lower ends of the via-holes to be electrically connected to a main board.  
   
   
       13 . The method according to  claim 11 , wherein the step b) comprises forming the metallic bonding agent while forming the metal dam on the lower wafer.  
   
   
       14 . The method according to  claim 11 , wherein at the step b), the metal layer is electrically connected to an inner ground terminal to prevent electromagnetic waves from being induced from the outside after plating the metal layer.  
   
   
       15 . The method according to  claim 11 , wherein the step c) comprises flip-chip bonding of the upper wafer to the lower wafer via the metallic bonding agent such that the input and output electrodes, and the IDT electrodes of the upper wafer face the input and output electrodes, and the IDT electrodes of the lower wafer, respectively.  
   
   
       16 . The method according to  claim 15 , wherein flip-chip bonding of the upper wafer to the lower wafer comprises supersonic bonding by use of stud bumps interposed between a conductive pad laid on the input and output electrodes of the upper wafer and another conductive pad laid on the input and output electrodes of the lower wafer.  
   
   
       17 . The method according to  claim 15 , wherein flip-chip bonding of the upper wafer to the lower wafer comprises thermal bonding by use of AuSn-based solder bumps interposed between a conductive pad laid on the input and output electrodes of the upper wafer and another conductive pad laid on the input and output electrodes of the lower wafer.  
   
   
       18 . The method according to  claim 11 , wherein at the step d), the separating grooves are formed to an extent that the upper surface of the lower wafer is exposed to the outside.  
   
   
       19 . The method according to  claim 11 , wherein, at the step e), the metal layer is plated by an electroplating process.