Correcting time synchronization inaccuracy caused by internal asymmetric delays in a device

Abstract

A method for time synchronization that avoids time synchronization inaccuracies caused by asymmetric delays internal to a device. Time synchronization according to the present teachings includes determining an asymmetry between an internal delay of an inbound timing packet in a device and an internal delay of an outbound timing packet in the device and correcting a time synchronization in response to the asymmetry.

1 . A method for time synchronization, comprising: 
 determining an asymmetry between an internal delay of an inbound timing packet in a device and an internal delay of an outbound timing packet in the device;    correcting a time synchronization in response to the asymmetry.    
   
   
       2 . The method of  claim 1 , wherein determining an asymmetry comprises: 
 measuring the internal delay of the inbound timing packet;    measuring the internal delay of the outbound timing packet.    
   
   
       3 . The method of  claim 2 , wherein measuring the internal delay of the inbound timing packet comprises; 
 generating a first timestamp in response to the inbound timing packet on a first portion of the communication link;    generating a second timestamp inside the device in response to the inbound timing packet.    
   
   
       4 . The method of  claim 3 , wherein measuring the internal delay of the outbound timing packet comprises; 
 generating a third timestamp inside the device in response to the outbound timing packet; generating a fourth timestamp in response to the outbound timing packet on a second portion of the communication link.    
   
   
       5 . The method of  claim 4 , wherein determining an asymmetry comprises determining the asymmetry in response to the first, second, third, and fourth timestamps.  
   
   
       6 . The method of  claim 1 , wherein determining an asymmetry comprises: 
 synchronizing a local clock in the device by exchanging a set of timing packets with a standard clock having a predetermined amount of internal delay asymmetry;    determining a difference between a time in the local clock and a time in the standard clock such that the difference provides an indication of the asymmetry.    
   
   
       7 . The method of  claim 6 , wherein exchanging a set of timing packets with a standard clock comprises exchanging the timing packets with the standard clock via a calibrated communication link.  
   
   
       8 . The method of  claim 6 , wherein determining a difference between a time in the local clock and a time in the standard clock comprises comparing a timing feature of the local clock to a timing feature of the standard clock.  
   
   
       9 . A system with time synchronization, comprising: 
 device having an asymmetry between an internal delay of an inbound timing packet in the device and an internal delay of an outbound timing packet in the device;    symmetric sampler for measuring the internal delays such that the measured internal delays enable a correction to a time synchronization for the device.    
   
   
       10 . The system of  claim 9 , wherein the symmetric sampler samples a time at which the inbound timing packet arrives at the device.  
   
   
       11 . The system of  claim 9 , wherein the symmetric sampler samples a time at which the outbound timing packet arrives at a communication link coupled to the device.  
   
   
       12 . The system of  claim 9 , wherein the symmetric sampler includes a local clock that synchronizes with the local clock in the device.  
   
   
       13 . The system of  claim 9 , wherein the symmetric sampler is coupled to the device via a communication link having a length that is selected to minimize an asymmetry associated with the communication link.  
   
   
       14 . The system of  claim 9 , wherein the symmetric sampler is coupled to the device via a communication link that is calibrated to minimize an asymmetry associated with the communication link.