Memory with memory cells that include a mim type capacitor with a lower electrode made for reduced resistance at an interface with a metal film

Abstract

A semiconductor device includes memory cells each having an MISFET for memory selection formed on one major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode electrically connected at a bottom portion to one of a source and drain of the MISFET for memory selection via a first metal layer and an upper electrode formed on the lower electrode via a capacitive insulating film. The lower electrode has a thickness of 30 nm or greater at the bottom portion thereof. Sputtering with a high ionization ratio and high directivity, such as PCM, is adapted to the formation of the lower electrode to make only the bottom portion of a capacitor thicker.

1 . A fabrication method for a semiconductor device comprising memory cells each having an MISFET for memory selection formed on one major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode electrically connected at a bottom portion to one of a source and drain of said MISFET for memory selection via a first metal layer and an upper electrode formed on said lower electrode via a capacitive insulating film, said method comprising the steps of: 
 forming an interlayer insulating film on said first metal layer;    boring a hole in said interlayer insulating film to expose said first metal layer at a bottom portion of said hole;    forming said lower electrode whose thickness at that portion which contacts the first metal layer at that portion which contacts the first metal layer is greater than a thickness of the other portion;    forming said capacitive insulating film;    reforming said capacitive insulating film; and    forming said upper electrode.    
   
   
       2 . A fabrication method for a semiconductor device comprising memory cells each having an MISFET for memory selection formed on one major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode electrically connected at a bottom portion to one of a source and drain of said MISFET for memory selection via a first metal layer and an upper electrode formed on said lower electrode via a capacitive insulating film, said method comprising the steps: 
 forming an interlayer insulating film on said first metal layer;    boring a hole in said interlayer insulating film to expose said first metal layer at a bottom portion of said hole;    forming said lower electrode whose thickness at that portion which contacts the first metal layer at that portion which contacts the first metal layer is greater than a thickness of the other portion;    forming said capacitive insulating film;    reforming said capacitive insulating film; and    forming said upper electrode.    
   
   
       3 . A fabrication method for a semiconductor device comprising memory cells each having an MISFET for memory selection formed on one major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode having a columnar shape having a cavity in a center portion thereof and electrically connected at a bottom portion to one of a source and drain of said MISFET for memory selection via a first metal layer and an upper electrode formed on said lower electrode via a capacitive insulating film, said method comprising the steps of: 
 forming an interlayer insulating film on said first metal layer;    boring a hole in said interlayer insulating film to expose said first metal layer at a bottom portion of said hole;    forming said lower electrode which satisfies a relationship of (a minimum distance between said cavity in said lower electrode and said first metal layer) ≧30 nm;    forming said capacitive insulating film;    reforming said capacitive insulating film; and    forming said upper electrode.    
   
   
       4 . The fabrication method according to  claim 3 , wherein said step of forming said lower electrode has a step of burying said hole bored in said interlayer insulating film with a film for forming said lower electrode in such a way as to satisfy a relationship of (a minimum distance between a cavity in said second metal layer and said first metal layer) ≧30 nm.  
   
   
       5 . The fabrication method according to any one of  claims 1  to  3 , wherein said step of boring a hole in said interlayer insulating film takes place once from said step of forming said interlayer insulating film to said step of forming said capacitive insulating film.  
   
   
       6 . The fabrication method according to any one of  claims 1  to  3 , wherein in said step of forming said lower electrode, the thickness of said lower electrode at the bottom portion thereof is greater than the thickness of said lower electrode at a side portion thereof.  
   
   
       7 . The fabrication method according to any one of  claims 1  to  3 , wherein in said step of forming said lower electrode, the thickness of said lower electrode at the bottom portion thereof is  30  nm or greater and the thickness of said lower electrode at the side portion thereof does not exceed at least  30  nm.  
   
   
       8 . The fabrication method according to any one of  claims 1  to  3 , wherein in said step of forming said lower electrode, the thickness of that portion of said lower electrode which contacts said first metal layer is greater than the thickness of the other portion.  
   
   
       9 . The fabrication method according to any one of  claims 1  to  3 , wherein in said step of forming said lower electrode, the thickness of at least that portion of said lower electrode which contacts said first metal layer is 30 nm or greater and the thickness of said lower electrode at the side portion thereof does not exceed at least 30 nm.  
   
   
       10 . A fabrication method for a semiconductor device which comprises memory cells each having an MISFET for memory selection formed on one major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode electrically connected at a bottom portion to one of a source and drain of said MISFET for memory selection via a first metal layer and a second metal layer and an upper electrode formed on said lower electrode via a capacitive insulating film in which said first metal layer and said second metal layer partly contact each other and said second metal layer partly contacts said lower electrode, said method comprising the steps of: 
 forming an interlayer insulating film on said first metal layer;    boring a hole in said interlayer insulating film to expose said first metal layer at a bottom portion of said hole;    forming said second metal layer in said bottom portion of said hole;    forming said lower electrode;    forming said capacitive insulating film;    reforming said capacitive insulating film; and    forming said upper electrode.    
   
   
       11 . The fabrication method according to  claim 10 , wherein in said step of forming said lower electrode, the thickness of at least that portion of said lower electrode which contacts said second metal layer is 30 nm or greater and the thickness of said lower electrode at the side portion thereof does not exceed at least 30 nm.  
   
   
       12 . The fabrication method according to  claim 10  or  11 , wherein said second metal layer is a titanium nitride film.  
   
   
       13 . The fabrication method according to any one of  claims 1  to  3  and  10 , wherein said first metal layer is a titanium nitride film.  
   
   
       14 . The fabrication method according to any one of  claims 1  to  3  and  10 , wherein said first metal layer is a tungsten film.  
   
   
       15 . The fabrication method according to any one of  claims 1  to  3  and  10 , wherein said lower electrode is a metal film.  
   
   
       16 . The fabrication method according to any one of  claims 1  to  3  and  10 , wherein said lower electrode is a ruthenium film.  
   
   
       17 . The fabrication method according to any one of  claims 1  to  3  and  10 , wherein said lower electrode is a titanium nitride film.  
   
   
       18 . The fabrication method according to any one of  claims 1  to  3  and  10 , wherein said capacitive insulating film includes a tantalum oxide film.  
   
   
       19 . The fabrication method according to any one of  claims 1  to  3  and  10 , wherein said upper electrode is a metal film.  
   
   
       20 . The fabrication method according to any one of  claims 1  to  3  and  10 , wherein said upper electrode is a ruthenium film.  
   
   
       21 . The fabrication method according to any one of  claims 1  to  3  and  10 , wherein said step of forming said lower electrode includes both a step of depositing a metal film by sputtering and a step of depositing a metal film by CVD.  
   
   
       22 . The fabrication method according to any one of  claims 1  to  3  and  10 , wherein said step of forming said lower electrode includes a step of depositing a metal film by PCM sputtering.  
   
   
       23 . The fabrication method according to any one of  claims 1  to  3  and  10 , wherein said step of forming said lower electrode includes a step of depositing a metal film by collimate sputtering.  
   
   
       24 . The fabrication method according to any one of  claims 1  to  3  and  10 , wherein said step of reforming said capacitive insulating film is a heat treatment step.  
   
   
       25 . The fabrication method according to any one of  claims 1  to  3  and  10 , wherein said step of reforming said capacitive insulating film is a heat treatment step which is performed in a hydrogen atmosphere.  
   
   
       26 . The fabrication method according to any one of  claims 1  to  3  and  10 , wherein said step of reforming said capacitive insulating film is a heat treatment step which is performed in an ozone atmosphere.  
   
   
       27 . The fabrication method according to any one of  claims 1  to  3  and  10 , wherein said step of reforming said capacitive insulating film is a heat treatment which is performed in an oxygen atmosphere at a temperature of 360° C. or higher and 460° C. or lower.