Method of manufacturing a multilayered doped conductor for a contact in an integrated circuit device

Abstract

A method of manufacturing a memory device addressing reliability and refresh characteristics through the use of a multilayered doped conductor, and a method making is described. The multilayered doped conductor creates a high dopant concentration in the active area close to the channel region. The rich dopant layer created by the multilayered doped conductor is less susceptible to depletion from trapped charges in the oxide. This improves device reliability at burn-in and lowers junction leakage, thereby providing a longer period between refresh cycles.

1 . A method of fabricating a memory integrated circuit device having a channel region less than 0.18 μm and a gate overlap less than 0.018 μm, comprising: 
 forming a gate electrode overlying a layer of field oxide over the surface of a semiconductor substrate;    providing lightly doped source/drain regions in said semiconductor substrate adjacent said gate electrode;    providing an insulating layer over the surface of said substrate;    providing an opening through said insulating layer to one of said lightly doped source/drain regions;    providing a conductor for said semiconductor substrate, wherein said conductor comprises, 
 a first conductive layer on said semiconductor substrate,  
 a first dopant within said first conductive layer, wherein first dopant comprises arsenic, antimony, or combinations thereof,  
 a second conductive layer adjacent said first conductive layer, and  
 a second dopant within said second conductive layer, said second dopant comprises phosphorus; and  
   continuing processing to form said memory integrated circuit device.    
     
     
         2 . The method of  claim 1 , wherein said first conductive layer is in said opening and in contact with said one of said lightly doped source/drain regions.  
     
     
         3 . The method of  claim 1 , wherein said first dopant diffusivity being less than said second dopant, said first dopant forming by solid state diffusion a shallow diffusion region in said one of the lightly doped source/drain regions beneath said conductor having a dopant concentration greater than said one of the lightly doped source/drain regions, and said second dopant providing a graded dopant concentration in a portion of said one of the lightly doped source/drain regions by diffusing below and adjacent said shallow diffusion region.  
     
     
         4 . The method of  claim 3  wherein said shallow diffusion region diffuses partially beneath said one of said spacer.  
     
     
         5 . The method of  claim 1 , wherein said conductor has a thickness of about 100 to about 1000 Angstroms for the first conductive layer.  
     
     
         6 . The method of  claim 1 , wherein said conductor has a thickness of about 2000 to about 2500 Angstroms for the second conductive layer.  
     
     
         7 . The method of  claim 1 , wherein said first conductive layer has an average dopant concentration for ranging from about 1×10 19  to about 1×10 21  ions/cm 3  of said first dopant.  
     
     
         8 . The method of  claim 1 , wherein said second conductive layer has an average dopant concentration ranging from about 1×10 19  to about 1×10 21  ions/cm 3  of said second dopant.  
     
     
         9 . The method of  claim 1  wherein said first dopant diffusivity is less than said second dopant.  
     
     
         10 . A method of fabricating a memory integrated circuit device having a channel region less than 0.18 μm and a gate overlap less than 0.018 μm, comprising: 
 forming a gate electrode overlying a layer of field oxide over the surface of a semiconductor substrate;    providing lightly doped source/drain regions in said semiconductor substrate adjacent said gate electrode;    providing an insulating layer over the surface of said substrate;    providing an opening through said insulating layer to one of said lightly doped source/drain regions;    providing a conductor for said semiconductor substrate, wherein said conductor comprises, 
 a first conductive layer on said semiconductor substrate,  
 a first dopant within said first conductive layer, said first dopant comprises boron, boron bifluoride, borane, or combination thereof,  
 a second conductive layer adjacent said first conductive layer, and  
 a second dopant within said second conductive layer, said second dopant comprises boron, boron bifluoride, borane, or combination thereof, and  
   continuing processing to form said memory integrated circuit device.    
     
     
         11 . The method of  claim 10  further comprising a doped region of the substrate under the first conductive layer.  
     
     
         12 . The method of  claim 11  further comprising a graded doped region of the substrate under said doped region.  
     
     
         13 . The method of  claim 11  wherein said doped region extends under the conductor to a depth of no greater than about 0.02 μm.  
     
     
         14 . The method of  claim 11  wherein a dopant concentration of said doped region concentration is greater than a dopant concentration a lightly doped region of said substrate.  
     
     
         15 . A method of fabricating a memory integrated circuit device having a channel region less than 0.18 μm and a gate overlap less than 0.018 μm, said method comprising: 
 providing a layer of a field oxide over the surface of a semiconductor substrate; 
 forming a gate electrode overlying a layer of field oxide;  
   providing lightly doped source/drain regions in said semiconductor substrate adjacent said gate electrode;    providing an insulating layer over the surface of said substrate;    providing an opening through said insulating layer to one of said lightly doped source/drain regions;    providing a conductor for said semiconductor substrate, wherein said conductor includes: 
 providing a first conductive layer on said semiconductor substrate,  
 proving a first dopant within said first conductive layer, said first dopant comprises arsenic, antimony, or combinations thereof,  
 providing a second conductive layer adjacent said first conductive layer, and  
 providing a second dopant within said second conductive layer, said second dopant diffusivity being greater that said first dopant and said second dopant comprises phosphorus;  
   providing a shallow, dopant portion in the semiconductor substrate adjacent to the channel region that addresses susceptible to depletion of trapped charges in the channel region of a semiconductor substrate; and    continuing processing to form said integrated circuit device.    
     
     
         16 . The method of  claim 15 , wherein said conductor is located adjacent a transistor.  
     
     
         17 . The method of  claim 15  wherein said first conductive layer lines a contact opening.  
     
     
         18 . A method of fabricating a memory integrated circuit device having a channel region less than 0.18 μm and a gate overlap less than 0.018 μm, said method comprising: 
 providing a layer of a field oxide over the surface of a semiconductor substrate; 
 forming a gate electrode overlying a layer of field oxide;  
   providing lightly doped source/drain regions in said semiconductor substrate adjacent said gate electrode;    providing an insulating layer over the surface of said substrate;    providing an opening through said insulating layer to one of said lightly doped source/drain regions;    providing a conductor for said semiconductor substrate, wherein said conductor includes: 
 providing a first conductive layer on said semiconductor substrate,  
 proving a first dopant within said first conductive layer, said first dopant comprises boron, boron bifluoride, borane, or combination thereof,  
 providing a second conductive layer adjacent said first conductive layer, and  
 providing a second dopant within said second conductive layer, said second dopant diffusivity being greater that said first dopant and said second dopant comprises boron, boron bifluoride, borane, or combination thereof,  
   providing a shallow, dopant portion in the semiconductor substrate adjacent to the channel region that addresses susceptible to depletion of trapped charges in the channel region of a semiconductor substrate; and    continuing processing to form said integrated circuit device.    
     
     
         19 . The method of  claim 18  wherein said first dopant diffusivity is less than said second dopant.  
     
     
         20 . The method of  claim 18 , wherein said first dopant diffusivity being less than said second dopant, said first dopant forming by solid state diffusion a shallow diffusion region in said one of the lightly doped source/drain regions beneath said conductor having a dopant concentration greater than said one of the lightly doped source/drain regions, and said second dopant providing a graded dopant concentration in a portion of said one of the lightly doped source/drain regions by diffusing below and adjacent said shallow diffusion region.