US2007155076A1PendingUtilityA1

Method for fabricating saddle type fin transistor

Assignee: HYNIX SEMICONDUCTOR INCPriority: Dec 29, 2005Filed: Jun 29, 2006Published: Jul 5, 2007
Est. expiryDec 29, 2025(expired)· nominal 20-yr term from priority
Inventors:Kwang-Ok Kim
H10P 50/73H10P 50/692H10P 50/691H10D 30/62H10D 30/024
50
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A method for fabricating a saddle type fin transistor includes: preparing a substrate where a device isolation structure is already formed; forming a hard mask pattern over the substrate, the hard mask pattern including a coating layer obtained through a coating method; and performing an etching process using the hard mask pattern as an etch mask to form a saddle type fin. The hard mask pattern may be formed in a stack structure including an amorphous carbon layer and the coating layer.

Claims

exact text as granted — not AI-modified
1 . A method for fabricating a saddle type fin transistor, comprising: 
 preparing a substrate where a device isolation structure is already formed;    forming a hard mask pattern over the substrate, the hard mask pattern including a coating layer obtained through a coating method; and    performing an etching process using the hard mask pattern as an etch mask to form a saddle type fin.    
   
   
       2 . The method of  claim 1 , wherein the hard mask pattern is formed in a stack structure including an amorphous carbon layer and the coating layer.  
   
   
       3 . The method of  claim 2 , wherein the amorphous carbon layer is formed over the coating layer.  
   
   
       4 . The method of  claim 2 , wherein the amorphous carbon layer is formed underneath the coating layer.  
   
   
       5 . The method of  claim 3 , wherein the coating layer includes an anti-reflective coating layer.  
   
   
       6 . The method of  claim 4 , wherein the coating layer includes an anti-reflective coating layer.  
   
   
       7 . The method of  claim 5 , wherein the coating layer is formed to a height larger than a height difference created beneath the hard mask pattern.  
   
   
       8 . The method of  claim 6 , wherein the coating layer is formed to a height larger than a height difference created beneath the hard mask pattern.  
   
   
       9 . The method of  claim 7 , wherein the forming of the hard mask pattern comprises: 
 forming a silicon oxynitride (SiON) layer over the hard mask pattern;    coating an anti-reflective coating layer over the SiON layer;    forming a photoresist pattern over the anti-reflective coating layer; and    performing a photolithography process on the photoresist pattern to sequentially etch the anti-reflective coating layer, the SiON layer and the hard mask pattern.    
   
   
       10 . The method of  claim 8 , wherein the forming of the hard mask pattern comprises: 
 forming a silicon oxynitride (SiON) layer over the hard mask pattern;    coating an anti-reflective coating layer over the SiON layer;    forming a photoresist pattern over the anti-reflective coating layer; and    performing a photolithography process on the photoresist pattern to sequentially etch the anti-reflective coating layer, the SiON layer and the hard mask pattern.

Join the waitlist — get patent alerts

Track US2007155076A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.