Nonvolatile semiconductor memory and method of manufacturing the same

Abstract

A nonvolatile semiconductor memory includes a first and a second diffusion layer regions, a floating gate electrode disposed, with a gate insulating film interposed therebetween, on a channel region between the first and second diffusion layer regions, and a control gate electrode serving as a word line and disposed on the floating gate electrode with an interelectrode insulating film interposed therebetween. The interelectrode insulating film covers whole side portions of the floating gate electrode located in a direction different from a direction in which the word line extends, and the control gate electrode covers the side portions of the floating gate electrode located in the direction different from the direction in which the word line extends.

1 . A nonvolatile semiconductor memory comprising: 
 a first and a second diffusion layer regions;    a floating gate electrode disposed, with a gate insulating film interposed therebetween, on a channel region between the first and second diffusion layer regions; and    a control gate electrode disposed on the floating gate electrode with an interelectrode insulating film interposed therebetween, the control gate electrode serving as a word line,    wherein the interelectrode insulating film covers whole side portions of the floating gate electrode, the control gate electrode covers the side portions of the floating gate electrode, and the side portions are located in a direction different from a direction in which the word line extends.    
   
   
       2 . The nonvolatile semiconductor memory according to  claim 1 , 
 wherein the interelectrode insulating film is in contact with the gate insulating film.    
   
   
       3 . The nonvolatile semiconductor memory according to  claim 1 , 
 wherein the control gate electrode covers a part of side portions of the floating gate electrode located in the direction in which the word line extends, with the interelectrode insulating film interposed therebetween.    
   
   
       4 . The nonvolatile semiconductor memory according to  claim 1 , 
 wherein an upper end of the floating gate electrode is aligned with an upper end of a device isolation insulating film.    
   
   
       5 . The nonvolatile semiconductor memory according to  claim 1 , 
 wherein the floating gate electrode is a polysilicon film.    
   
   
       6 . The nonvolatile semiconductor memory according to  claim 1 , 
 wherein the control gate electrode is a polysilicon film.    
   
   
       7 . The nonvolatile semiconductor memory according to  claim 1 , 
 wherein the interelectrode insulating film is an ONO film.    
   
   
       8 . The nonvolatile semiconductor memory according to  claim 1 , 
 wherein the interelectrode insulating film is a high-dielectric film.    
   
   
       9 . The nonvolatile semiconductor memory according to  claim 1 , 
 wherein the first and second diffusion layer regions include a shallow diffusion layer region and a deep diffusion layer region.    
   
   
       10 . A NAND flash memory including the nonvolatile semiconductor memory according to  claim 1 .  
   
   
       11 . A two-transistor flash memory including the nonvolatile semiconductor memory according to  claim 1 .  
   
   
       12 . A method of manufacturing a nonvolatile semiconductor memory comprising: 
 forming a pattern of a floating gate electrode;    forming an interelectrode insulating film covering a surface of the floating gate electrode;    forming an underlayer on the interelectrode insulating film, the underlayer having a buldging portion above the floating gate electrode;    forming a first mask layer on the underlayer;    flattening the buldging portion;    forming a pattern of the first mask layer in a self-alignment manner, the pattern of the first mask layer having a first opening above the floating gate electrode;    forming a second opening by etching the underlayer, with the first mask layer used as a mask, until the interelectrode insulating film is exposed;    forming a conductive film on the interelectrode insulating film exposed in the second opening, the conductive film having a depressed portion above the floating gate electrode;    forming a second mask layer on the conductive film;    forming a pattern of the second mask layer in the depressed portion in a self-alignment manner, by etching the second mask layer; and    forming a control gate electrode by etching the conductive film, with the second mask layer used as a mask.    
   
   
       13 . The method of manufacturing a nonvolatile semiconductor memory according to  claim 12 , 
 wherein the underlayer is a polysilicon film.    
   
   
       14 . The method of manufacturing a nonvolatile semiconductor memory according to  claim 12 , 
 wherein the first mask layer is a silicon oxide film.    
   
   
       15 . The method of manufacturing a nonvolatile semiconductor memory according to  claim 12 , 
 wherein the second mask layer is a silicon nitride film.    
   
   
       16 . A method of manufacturing a nonvolatile semiconductor memory comprising: 
 forming a pattern of a floating gate electrode;    forming an interelectrode insulating film covering a surface of the floating gate electrode;    forming a conductive film on the interelectrode insulating film;    forming an underlayer on the conductive film, the underlayer having a buldging portion above the floating gate electrode;    forming a first mask layer on the underlayer;    flattening the buldging portion, and forming a pattern of the first mask layer in a self-alignment manner, the pattern of the first mask layer having a first opening above the floating gate electrode;    forming a second opening by etching the underlayer, with the first mask layer used as a mask, until the conductive film is exposed;    forming a second mask layer on the conductive film exposed in the second opening;    forming a pattern of the second mask layer in the second opening in a self-alignment manner, by etching the second mask layer; and    forming a control gate electrode by etching the underlayer and the conductive film, with the second mask layer used as a mask.    
   
   
       17 . The method of manufacturing a nonvolatile semiconductor memory according to  claim 16 , 
 wherein the underlayer is a silicon oxide layer.    
   
   
       18 . The method of manufacturing a nonvolatile semiconductor memory according to  claim 16 , 
 wherein each of the first and second mask layers is a silicon nitride film.    
   
   
       19 . A method of manufacturing a nonvolatile semiconductor memory comprising: 
 forming a stacked gate electrode of a memory cell transistor;    forming a conductive film covering the stacked gate electrode of the memory cell transistor;    forming a mask layer on the conductive film;    forming a pattern of the mask layer in a self-alignment manner by etching the mask layer, the pattern of the mask layer being adjacent to the conductive film located on side portions of the stacked gate electrode of the memory cell transistor; and    forming a gate electrode of a select transistor by etching the conductive film with the mask layer used as a mask.    
   
   
       20 . The method of manufacturing a nonvolatile semiconductor memory according to  claim 19 , 
 wherein the conductive film is a polysilicon film.