Memory Module Having a Clock Line and Termination

Abstract

A memory system includes a controller chip and a memory module coupled to the controller chip. A signal line carries a signal that traverses the signal line until reaching a termination at an end of the signal line. A clock line carries a clock signal that traverses the clock line to reach a second termination at an end of the clock line. The module includes a first memory device connected to the signal line and the clock line such that the signal and the clock signal arrive at the first memory device at substantially the same time. The module includes a second memory device connected to the signal line and the clock line such that the signal and the clock signal arrive at the second memory device at substantially the same time and after the signal and the clock signal arrive at the first memory device.

1 . A system comprising: 
 a controller chip; and    a memory module coupled to the controller chip, the memory module comprising:    a first signal line coupled to the controller chip, the first signal line to carry a first signal between a first end of the first signal line and a second end of the first signal line, wherein the first signal enters the module at the first end of the first signal line, the first signal traversing the first signal line until reaching a first termination at the second end of the first signal line;    a clock line to carry a clock signal between a first end of the clock line and a second end of the clock line, wherein the clock signal enters the module at the first end of the clock line and traverses the clock line alongside the first signal until the clock signal reaches a second termination at the second end of the clock line;    a first memory device connected to the first signal line and the clock line such that the first signal and the clock signal arrive at the first memory device at substantially the same time; and    a second memory device connected to the first signal line and the clock line such that the first signal and the clock signal arrive at the second memory device at substantially the same time and after the first signal and the clock signal arrive at the first memory device.    
   
   
       2 . The system of  claim 1 , further comprising: 
 a second signal line to carry a second signal between a first end of the second signal line and a second end of the second signal line, wherein the second signal enters the module at the first end of the second signal line, the second signal traversing the second signal line until reaching a third termination at the second end of the second signal line.    
   
   
       3 . The system of  claim 2 , wherein the first signal and the second signal arrive at the first memory device at substantially the same time, and the first signal and the second signal arrive at the second memory device at substantially the same time.  
   
   
       4 . The system of  claim 2 , wherein the first signal line and second signal line have substantially equal electrical length.  
   
   
       5 . The system of  claim 2 , wherein each of the first signal line and second signal line include a right angled turn at a feed-through hole in a substrate of the module.  
   
   
       6 . The system of  claim 2 , wherein the first and second signal lines carry address and control information.  
   
   
       7 . The system of  claim 2 , wherein the first and second signal lines and the clock line have substantially equal electrical length.  
   
   
       8 . The system of  claim 7 , further comprising a first plurality of edge fingers, wherein the first end of the first signal line is connected to a first edge finger of the first plurality of edge fingers and the first end of the second signal line is connected to a second edge finger of the first plurality of edge fingers.  
   
   
       9 . The system of  claim 8 , further comprising a second plurality of edge fingers, the second plurality of edge fingers interleaved with the first plurality of edge fingers, the second plurality of edge fingers connected to a reference plane disposed within the module, wherein the reference plane is a ground potential reference plane.  
   
   
       10 . The system of  claim 9 , further comprising a clock generator device coupled to the first end of the clock line, the clock generator device to generate the clock signal.  
   
   
       11 . A system having a socket to receive a memory module, the memory module comprising: 
 a substrate;    a first plurality of edge fingers disposed at an edge of the substrate;    a plurality of signal lines routed along the length of the substrate, wherein each signal line of the plurality of signal lines is connected to an edge finger of the first plurality of edge fingers, wherein each signal line of the plurality of signal lines has a respective end coupled to a termination device;    a plurality of memory devices disposed on the substrate, wherein each memory device of the plurality of memory devices is connected to the plurality of signal lines such that signals traversing along the plurality of signal lines arrive at the plurality of memory devices in sequence before reaching the termination device; and    a clock line routed alongside the plurality of signal lines, the clock line to carry a clock signal that propagates alongside a plurality of signals traversing along the plurality of signal lines, wherein each signal line of the plurality of signal lines and the clock line have substantially equal electrical length.    
   
   
       12 . The system of  claim 11 , wherein the signals traversing along the plurality of signal lines includes a first signal traversing along a first signal line of the plurality of signal lines and a second signal traversing along a second signal line of the plurality of signal lines, and wherein the first signal and the second signal arrive substantially uniformly at each memory device of the plurality of memory devices.  
   
   
       13 . The system of  claim 12 , wherein the first and second signal lines have substantially equal electrical length.  
   
   
       14 . The system of  claim 12 , wherein each of the first and second signal lines includes a right angled turn at a feed-through hole in the substrate.  
   
   
       15 . The system of  claim 12 , wherein the first and second signal lines carry address and control information.  
   
   
       16 . The system of  claim 11 , further comprising 
 a reference plane disposed within the memory module; and    a second plurality of edge fingers, wherein edge fingers of the second plurality of edge fingers are interleaved with edge fingers of the first plurality of edge fingers, the second plurality of edge fingers are connected to the reference plane disposed within the memory module.    
   
   
       17 . The system of  claim 16 , wherein the reference plane is a ground potential reference plane.  
   
   
       18 . A computer motherboard having a socket to receive a module, the module comprising: 
 a signal line having a first end and a second end;    a first termination device connected to the second end of the signal line, wherein a signal enters the module at the first end of the signal line, traverses the signal line, and terminates at the first termination device;    a clock line having a first end and a second end, wherein the clock line is routed alongside the signal line, the clock line to carry a clock signal that propagates alongside the signal that traverses the signal line, wherein the clock line and the signal line have substantially equal length; and    a second termination device connected to the second end of the clock line, wherein the clock signal enters the module at the first end of the clock line, traverses the clock line and terminates at the second termination device.    
   
   
       19 . The motherboard of  claim 18 , wherein the module further comprises: 
 a plurality of edge fingers, wherein the signal line is connected to an edge finger of the plurality of edge fingers, and wherein the first end of the clock line is connected to an edge finger of the plurality of edge fingers.    
   
   
       20 . A system comprising: 
 a circuit board; and    a socket, disposed, on the circuit board, to receive a memory module, the module comprising: 
 a signal line that includes a first end and a second end, and a clock line routed alongside the signal line, the clock line including a first end and a second end, wherein a signal enters the module at a first end of the signal line, traverses the signal line, and terminates at a first termination device, the clock line to carry a clock signal that propagates alongside the signal that traverses the signal line, wherein the signal line has a first length between the first end and second end of the signal line, and the clock line has a second length between the first end and second end of the clock line, wherein the first length is substantially equal to the second length.  
   
   
   
       21 . The system of  claim 20 , wherein the memory module includes a plurality of signal lines, including said signal line, and the plurality of signal lines and the clock line have substantially equal electrical length.  
   
   
       22 . The system of  claim 21 , wherein each signal line of the plurality of signal lines includes a right angled turn at a feed-through hole in a substrate of the module.  
   
   
       23 . The system of  claim 21 , wherein the plurality of signal lines carry address and control information.  
   
   
       24 . The system of  claim 21 , further comprising: 
 a first plurality of edge fingers connected to the plurality of signal lines;    a second plurality of edge fingers, wherein the second plurality of edge fingers is interleaved with the first plurality of edge fingers; and    a reference plane disposed within the memory module and connected to the second plurality of edge fingers, wherein the reference plane is a ground potential reference plane.    
   
   
       25 . The system of  claim 21 , wherein the memory module includes memory devices disposed on the module and connected to the plurality of signal lines, wherein signals traversing along each signal line of the plurality of signal lines arrive at the memory devices in sequence before reaching a termination device connected to a second end of the signal line.  
   
   
       26 . A method of operation in a system comprising a memory module having a plurality of signal lines, a clock line routed alongside the plurality of signal lines, a first termination connected to a respective end of the plurality of signal lines, a second termination connected to an end of the clock line, and a plurality of memory devices, the method comprising: 
 traversing signals along the plurality of signal lines such that the signals arrive substantially uniformly at each memory device of the plurality of memory devices in sequence before reaching the first termination; and    traversing a clock signal along the clock line such that the clock signal traverses alongside the signals traversing along the plurality of signal lines, the clock signal starting at a first end of the clock line and terminating at the second termination.    
   
   
       27 . The method of  claim 26 , wherein a first signal of the plurality of signals arrives at a first memory device of the plurality of memory devices before arriving at a second memory device the plurality of memory devices, and wherein the first signal arrives at the second memory device before reaching the first termination, and wherein a second signal of the plurality of signals arrives at the first memory device before arriving at the second memory device and the second signal arrives at the second memory device before reaching the first termination.  
   
   
       28 . The method of  claim 27 , wherein the first signal and the second signal arrive at the first memory device at substantially the same time, and the first signal and the second signal arrive at the second memory device at substantially the same time and after the first signal and the second signal arrive at the first memory device.  
   
   
       29 . The method of  claim 26 , wherein the plurality of signal lines and the clock line have substantially equal electrical length.  
   
   
       30 . The method of  claim 26 , wherein each of the plurality of signal lines includes a right angled turn at a feed-through hole in a substrate of the module.  
   
   
       31 . The method of  claim 26 , wherein the plurality of signal lines carry address and control information.