Data transfer apparatus, storage device control apparatus and control method using storage device control apparatus

Abstract

A data transfer apparatus includes a memory having first and second queues for storing data transfer information that includes information specifying a first memory area and information specifying a second memory area, a first processor which registers the data transfer information in the first or second queue, and a second processor performing a processing to transfer data stored in the first memory area to the second memory area. The second processor reads out the data transfer information registered in the first queue, transfers the data based on the read data transfer information, and decides if data transfer information succeeding to the read data transfer information is registered in the first queue. If the succeeding data transfer information is registered, the second processor reads out the succeeding data transfer information from the first queue, and performs the data transfer processing based on the read data transfer information.

1 - 7 . (canceled)  
   
   
       8 . A storage device control apparatus comprising: 
 a communications interface unit having a buffer memory for receiving a data input/output request transmitted from an information processing apparatus to a storage device and storing said received data input/output request;    a storage device interface unit for transmitting and receiving data to/from said storage device;    a random access memory (RAM) having a preferential transfer information queue and a non-preferential transfer information queue for registering data transfer information that includes information for specifying a memory area of said buffer memory and information for specifying a memory area of said storage device, said preferential transfer information queue having a higher transfer priority than said non-preferential transfer information queue;    a central processing unit (CPU) for causing said data transfer information to be registered in said preferential transfer information queue or said non-preferential transfer information queue; and    a direct memory access (DMA) controller that performs data transfer processing to transfer data between said buffer memory and said storage device, said DMA controller having start and abort registers, wherein    said DMA controller reads out said data transfer information registered in said preferential transfer information queue, performs said data transfer processing on a basis of said read data transfer information, and decides if subsequent data transfer information that follows said read data transfer information is registered in said preferential transfer information queue,    if said subsequent data transfer information is registered in said preferential transfer information queue, said DMA controller reads out said subsequent data transfer information from said preferential transfer information queue, and performs said data transfer processing on a basis of said read data transfer information, and    if said subsequent data transfer information is not registered in said preferential transfer information queue, said DMA controller reads out said data transfer information from said non-preferential transfer information queue, and performs said data transfer processing on a basis of said read data transfer information from said non-preferential transfer information queue.    
   
   
       19 . A storage device control apparatus according to  claim 8 , wherein said RAM further comprises an end status queue for registering an end status of a data transfer processing by said DMA controller in response to completion of the data transfer processing, and said CPU checks the end status to inform abnormality of data transfer processing.  
   
   
       10 . A storage device control apparatus according to  claim 8 , wherein in response to detection of the subsequent data transfer information from said preferential transfer information queue or said non-preferential transfer information queue, said DMA controller continues a data transfer processing corresponding to the subsequent data transfer information independently of writing into the start register.