Connection verification apparatus for verifying interconnection between multiple logic blocks

Abstract

A connection verification apparatus verifies interconnection between a plurality of logic blocks constituting a semiconductor integrated circuit or the like. It includes a connection verification section for verifying interconnection between a first logic block and a second logic block by comparing a signal level of an output terminal of the first logic block with a signal level of an input terminal of the second logic block connected to the output terminal of the first logic block. The connection verification apparatus can verify the interconnection between the two logic blocks without verifying the logic processing to the two logic blocks.

1 . A connection verification method comprising the steps of: 
 receiving a signal level from an output terminal of a first logic block;    receiving a signal level from an input terminal of a second logic block connected to the output terminal of said first logic block, wherein said first and second logic blocks constitute a semiconductor integrated circuit; and    verifying interconnection between said first logic block and said second logic block by comparing the signal level supplied from said first input section with the signal level supplied from said second input section.    
   
   
       2 . The connection verification method according to  claim 1 , further comprising the steps of: 
 generating a test signal for connection verification; and    supplying the test signal to the output terminal of said first logic block.    
   
   
       3 . The connection verification method according to  claim 1 , further comprising the step of: 
 inhibiting logic operation of at least one of said first logic block and said second logic block when a connection imperfection between said first logic block and second logic block is detected at said verifying step.    
   
   
       4 . The connection verification method according to  claim 1 , further comprising the step of: 
 displaying information about the connection imperfection detected at said verifying step.    
   
   
       5 . The connection verification method according to  claim 1 , wherein said signal level from the output terminal of the first logic block and said signal level from the input of the second logic block are received in synchronization with a synchronizing signal.  
   
   
       6 . The connection verification method according to  claim 1 , further comprising the step of: 
 defining correspondence between the output terminal of said first logic block and the input terminal of said second logic block, wherein    referring a definition contents of said defining, said signal level supplied from the output terminal of the first logic block is compared with said signal level supplied from the input terminal of the second logic block at said verifying step.    
   
   
       7 . The connection verification method according to  claim 1 , wherein at least one of function verification and logic verification of said first logic block and said second logic block is carried out at the verifying step, after completing connection verification between said first logic block and said second logic block.  
   
   
       8 . A connection verification method comprising the steps of: 
 generating a test signal for connection verification, and supplying the test signal to an output terminal of a first logic block;    receiving a signal level from an input terminal of a second logic block connected to the output terminal of said first logic block, wherein said first and second logic blocks constitute a semiconductor integrated circuit; and    verifying interconnection between said first logic block and said second logic block by comparing a signal level of the test signal generated at said generating step with the signal level supplied at said receiving step.    
   
   
       9 . The connection verification method according to  claim 8 , further comprising the step of: 
 inhibiting logic operation of at least one of said first logic block and said second logic block when a connection imperfection between said first logic block and said second logic block is detected at said verifying step.    
   
   
       10 . The connection verification method according to  claim 8 , further comprising the step of: 
 displaying information about the connection imperfection detected in said verifying step.    
   
   
       11 . The connection verification method according to  claim 8 , wherein the test signal is supplied to the output terminal of said first logic block in synchronization with a synchronizing signal, the signal level is received in synchronization with the synchronizing signal at said receiving step.  
   
   
       12 . The connection verification method according to  claim 8 , further comprising the step of: 
 defining correspondence between the output terminal of said first logic block and the input terminal of said second logic block, wherein    referring to definition contents of said defining step, the signal level of the test signal supplied from the output terminal of the first logic block is compared with the signal level supplied from the input terminal of the second logic block at said verifying step.    
   
   
       13 . The connection verification method according to  claim 8 , wherein at least one of function verification and logic verification of said first logic block and said second logic block is carried out at the verifying step, after completing the connection verification between said first logic block and said second logic block.