Architectures for self-contained, mobile memory programming

Abstract

A computer system comprising: a plurality of memories each containing one or more locations; and a first threadlet for causing a first program to run in the computer system when at least one first memory location of the plurality of memory locations is local to the threadlet. Also provided is a method allowing such a threadlet to move itself to memories that include some specified second memory location.

1 - 36 . (canceled)  
   
   
       37 . A computer system comprising: 
 at least one first node connected to at least one second node, wherein said at least one first node and said at least one second node have at least one first memory and at least one second memory, respectively;    a threadlet configured to cause a program to run in said computer system executed by said at least one first node such that said at least one first memory is local to said threadlet; and    a parcel for moving said threadlet from said at least one first memory to said at least one second memory to execute said threadlet by said at least one second node when said at least one second memory is local to said threadlet.    
   
   
       38 . The computer system of  claim 37 , wherein said program requires access to a first memory location to run.  
   
   
       39 . The computer system of  claim 38 , wherein said threadlet is capable of determining that whether or not said first memory location is local to said threadlet.  
   
   
       40 . The computer system of  claim 37 , wherein said computer system is capable of saving said threadlet and a state of said threadlet in said parcel.  
   
   
       41 . The computer system of  claim 40 , wherein said state includes a program counter that references said program.  
   
   
       42 . The computer system of  claim 41 , wherein said computer system is capable of injecting said parcel into a communication network.  
   
   
       43 . The computer system of  claim 42 , wherein said computer system is capable of determining that said parcel has reached said second node after being injected into said communication network.  
   
   
       44 . The computer system of  claim 43 , wherein said computer system is, capable of unpacking said state from said parcel and restarting said threadlet in said state when said threadlet reaches said second node.  
   
   
       45 . The computer system of  claim 39 , wherein said computer system is capable of verifying that said first memory location is within said second node.  
   
   
       46 . The computer system of  claim 37 , wherein said threadlet includes said program.  
   
   
       47 . The computer system of  claim 37 , wherein said computer system includes a plurality of said first nodes and each first memory of each of said first nodes includes a copy of said program.  
   
   
       48 . The computer system of  claim 37 , wherein said program comprising an additional threadlet for causing said program to run in said computer system executed by said at least one first node when said at least one first memory is local to said additional threadlet; and wherein said parcel moves said additional threadlet from said at least one first memory to said at least one second memory to execute said additional threadlet by said at least one second node when said at least one second memory is local to said additional threadlet.  
   
   
       49 . The computer system of  claim 37 , wherein a minimum state of said threadlet is a wide word.  
   
   
       50 . The computer system of  claim 37 , wherein said threadlet has an extended state of full word plus a wide word.  
   
   
       51 . The computer system of  claim 37 , wherein said first node is on a PIM-enhanced memory chip.  
   
   
       52 . The computer system of  claim 37 , wherein said at least one first node is a plurality of first nodes.  
   
   
       53 . The computer system of  claim 52 , wherein each of said first nodes is on a PIM-enhanced memory chip.  
   
   
       54 . The computer system of  claim 52 , wherein each of said first nodes is on a set of PIM-enhanced memory chips interconnected by a communication network.  
   
   
       55 . A method comprising the steps of: 
 executing a program having a threadlet;    executing said threadlet by a first node such that a target memory required to execute said program at said first node is local to said threadlet; and    moving said threadlet to a second node such that said target memory required to execute said program at said second node is local to said threadlet.    
   
   
       56 . The method of  claim 55 , wherein said threadlet is capable of determining whether or not said target memory is local to said first threadlet.  
   
   
       57 . The method of  claim 55 , further comprising saving said threadlet and a state of said threadlet in a parcel.  
   
   
       58 . The method of  claim 57 , wherein said state includes a program counter that references said program.  
   
   
       59 . The method of  claim 57 , further comprising injecting said parcel into a communication network.  
   
   
       60 . The method of  claim 59 , wherein said computer system determines if said parcel has reached said second node after being injected into said communication network.  
   
   
       61 . The method of  claim 60 , further unpacking said state from said parcel and restarting said threadlet in said state when said threadlet reaches said second node.  
   
   
       62 . The method of  claim 61 , further comprising verifying that said target memory is within said second node.  
   
   
       63 . The method of  claim 55 , wherein said threadlet includes said program.  
   
   
       64 . The method of  claim 55 , wherein said program comprises an additional threadlet.  
   
   
       65 . The method of  claim 55 , wherein a minimum state of said threadlet is a wide word.  
   
   
       66 . The method of  claim 55 , wherein said threadlet has an extended state of full word plus a wide word.  
   
   
       67 . The method of  claim 55 , wherein said first node is on a PIM-enhanced memory chip.  
   
   
       68 . The method of  claim 55 , wherein said at least one first node is a plurality of first nodes.  
   
   
       69 . The method of  claim 68 , wherein each of said first nodes is on a PIM-enhanced memory chip.  
   
   
       70 . The method of  claim 68 , wherein each of said first nodes is on a set of PIM-enhanced memory chips interconnected by a communication network.  
   
   
       71 . The method of  claim 55 , further comprising suspending said threadlet at said second node when said threadlet determines that said threadlet is not the next operation for said program.  
   
   
       72 . The method of  claim 64 , further comprising the steps of: executing said additional threadlet by said first node when said target memory required to execute said program at said first node is local to said additional threadlet; and moving said threadlet to said second node when said target memory required to execute said program at said second node is local to said additional threadlet.