Hardware acceleration for a software transactional memory system

Abstract

A method and apparatus for accelerating transactional execution. Barriers associated with shared memory lines reference by memory accesses within a transaction are only invoked/executed the first time the shared memory lines are accessed within a transaction. Hardware support, such as a transaction field/transaction bits, are provided to determine if an access is the first access to a shared memory line during a pendancy of a transaction. Additionally, in an aggressive operational mode version numbers representing versions of elements stored in shared memory lines are not stored and validated upon commitment to save on validation cost. Moreover, even in a cautious mode, that stores version numbers to enable validation, validation costs may not be incurred, if eviction of accessed shared memory lines do not occur during execution of the transaction.

1 . An apparatus comprising: 
 a shared memory including a plurality of shared lines;    an execution module to execute a plurality of operations grouped into a transaction, wherein one of the plurality of operations includes an access to a shared line of the plurality of shared lines;    a lock module, when invoked, to check the state of a meta-data location associated 
 with the shared line; and  
   an acceleration module to 
 invoke the lock module, if the access to the shared line is the first access to the shared line during execution of the transaction, and  
 allow access to the cache line, without invoking the lock module, if the access to the shared line is not the first access to the shared line during execution of the transaction.  
   
     
     
         2 . The apparatus of  claim 1 , further comprising an eviction tracking module to abort the transaction, if the eviction tracking module is operating in an aggressive mode and tracks an eviction notification during execution of the transaction, and to validate the transaction, if the eviction tracking module is operating in a cautious mode and tracks an eviction notification during execution of the transaction.  
     
     
         3 . The apparatus of  claim 2 , wherein the eviction tracking module comprises: 
 logic to generate the eviction notification, wherein the eviction notification represents an access selected from a group consisting of an eviction of the shared memory line by a remote resource, an eviction of the shared memory line due to capacity constraints, an eviction of the shared memory line due to a snoop to the shared memory line by a remote resource, and an eviction of the shared memory line due to an access to the shared memory line invalidating a copy of the shared memory line stored in a transaction memory set associated with the transaction, and    a handler to abort the transaction based on the eviction notification, if the eviction tracking module is operating in the aggressive mode, and to validate the transaction based on the eviction notification, if the eviction tracking module is operating in the cautious mode.    
     
     
         4 . The apparatus of  claim 1 , wherein the meta-data location is a lock.  
     
     
         5 . The apparatus of  claim 4 , wherein the lock is in an array of locks, and wherein the lock indexed in the array of locks through a hash value of an address referencing the shared memory line.  
     
     
         6 . The apparatus of  claim 5 , wherein the state of the lock is a first owned state, which is represented by a first value stored in the lock, if the lock is owned, and the state of the lock is a second un-owned state, which is represented by a second version value stored in the lock, if the lock is not owned.  
     
     
         7 . The apparatus of  claim 6 , wherein the first value is an even integer, and wherein the second version value is an odd integer.  
     
     
         8 . The apparatus of  claim 6 , wherein the lock module, by default, is to operate in an aggressive mode, and wherein the lock module is to operate in a cautious mode, if the transaction is aborted a first number of times.  
     
     
         9 . The apparatus of  claim 8 , wherein the lock module, when operating in the aggressive mode, is to acquire the lock and not to store the second version value in a local transaction memory set, after checking the state of the lock, if the lock is in the second un-owned state.  
     
     
         10 . The apparatus of  claim 8 , wherein the lock module, when operating in the cautious mode, is to 
 acquire the lock and store the second version value in a local transaction memory set, after checking the state of the lock, if the lock is the second un-owned state, and    validate the stored second version value, upon committing the transaction.    
     
     
         11 . The apparatus of  claim 1 , wherein the acceleration module is also to determine if the access to the shared line is the first access to the shared line during execution of the transaction, and wherein determining if the access to the shared line is the first access to the shared line during execution of the transaction comprises: 
 checking a transaction bit associated with the shared memory line, wherein the transaction bit represents a first value, if the shared memory line has not been accessed during execution of the transaction, and the transaction bit represents a second value, if the shared memory line has been previously accessed during execution of the transaction.    
     
     
         12 . The apparatus of  claim 11 , wherein allowing access to the cache line, without invoking the lock module, if the access to the shared line is not the first access to the shared line during execution of the transaction comprises: providing the cache line to the execution module, without invoking the lock module to check the state of the lock, if the transaction bit represents the second value.  
     
     
         13 . The apparatus of  claim 11 , wherein the transaction bit is associated with the shared memory line through being a bit within the shared memory line.  
     
     
         14 . The apparatus of  claim 1 , wherein the shared memory is a cache memory shared between at least two resources present on a microprocessor, and wherein the execution module includes a fixed point unit to perform fixed data point operations and a floating point unit to perform floating data point operations.  
     
     
         15 . An apparatus comprising: 
 a processor including 
 a cache memory including a plurality of cache lines;  
 execution resources to execute a transaction, the transaction including a first instruction to access a first cache line of the plurality of cache lines, which is associated with a first transaction field and a first lock;  
 an acceleration module to 
 check a state of the first lock before the access to the first cache line, if the first transaction field represents a first value,  
 not check the state of the first lock before the access to the first line, if the first transaction field represents a second value, and  
 set the first transaction field to represent the second value upon the access to the first cache line, if the access is the first access to the first cache line during execution of the transaction.  
 
   
     
     
         16 . The apparatus of  claim 15 , wherein each cache line of the plurality of cache lines is capable to store a plurality of elements, and wherein the first transaction field includes a plurality of transaction bits, each of the transaction bits corresponding to one of the plurality of elements in the first cache line.  
     
     
         17 . The apparatus of  claim 16 , wherein each of the plurality of elements is individually selected from a group consisting of an instruction, an operand, and a grouping of logical values, and wherein the first cache line is associated with a first lock through mapping at least one element of the plurality of elements in the first cache line to the first lock.  
     
     
         18 . The apparatus of  claim 15 , wherein the first cache line is associated with the first lock through a hash table, the first lock being indexed in the hash table with a portion of an address referencing the first cache line.  
     
     
         19 . The apparatus of  claim 15 , wherein the first transaction field includes a transaction bit, and wherein the first value is a high logical value and the second value is a low-logical value.  
     
     
         20 . The apparatus of  claim 15 , wherein the first instruction is a load instruction, and wherein the acceleration module, when operating in a first mode, does not store a local copy of a version number stored in the first lock, upon acquiring the first lock, and when operating in a second mode, stores a local copy of a version number stored in the first lock, upon acquiring the first lock.  
     
     
         21 . The apparatus of  claim 20 , wherein the processor further includes a commitment module, the commitment module to 
 validate the local copy of the version number to determine if the first line is evicted before the transaction is committed, if the acceleration module is operating in the second mode; and    reset the first transaction field to the first value, upon committing the transaction.    
     
     
         22 . The apparatus of  claim 15 , wherein the execution resources are also to execute a handler routine to abort the transaction, if the first line is evicted before the transaction is committed, and wherein the handler routine is capable of rolling back nested transactions at a granularity of one transaction.  
     
     
         23 . The apparatus of  claim 15 , wherein the processor is selected from a group consisting of a host processor, a microprocessor, a processing core, a logical processor, and an embedded processor, a multi-threaded processor, and a multi-core processor.  
     
     
         24 . A system comprising: 
 a multiple-resource microprocessor including a cache memory including a plurality of cache lines; 
 an execution unit to execute a transaction, the transaction including a plurality of accesses to a cache line of the plurality of cache lines;  
 an acceleration module to 
 re-vector execution, by the execution unit, to a barrier associated with the cache line, upon a first access of the plurality of accesses to the cache line during a pendancy of the transaction, and  
 allow a subsequent access of the plurality of accesses to the cache line during the pendancy of the transaction, without re-vectoring execution to the barrier associated with the cache line;  
 
   a system memory coupled to the multi-resource microprocessor to store elements to be loaded into the plurality of cache lines in the cache memory.    
     
     
         25 . The system of  claim 24 , wherein each resource of the multiple resources in the multiple-resource processor is selected from a group consisting of a processor core, a logical processor, a processor thread, and a physical processor, and wherein the system memory is a memory device selected from a group consisting of a static random access memory (SRAM), dynamic random access memory (DRAM), a double data rate random access memory (DDR RAM), and a buffered random access memory (RAM).  
     
     
         26 . The system of  claim 24 , wherein re-vectoring execution by the execution unit to a barrier associated with the cache line includes 
 setting a carry flag to a first value, if the cache line has not been accessed a first time during pendancy of the transaction;    inspecting the carry flag; and    calling a handler, after inspecting the carry flag, to re-vector execution by the execution unit to the barrier, if the carry flag represents the first value.    
     
     
         27 . The system of  claim 24 , wherein re-vectoring execution by the execution unit to a barrier associated with the cache line includes 
 generating an interrupt, if the cache line has not been accessed a first time during pendancy of the transaction; and    handling the interrupt with a handler, the handler to re-vector execution by the execution unit to the barrier.    
     
     
         28 . The system of  claim 27 , wherein determining if the cache line has been accessed a first time during pendancy of the transaction includes: 
 checking a transaction bit associated with the cache line;    determining the cache line has been accessed a first time during pendancy of the transaction, if the transaction bit represents a first logical value; and    determining the cache line has not been accessed a first time during pendancy of the transaction, if the transaction bit represents a second logical value.    
     
     
         29 . The system of  claim 28 , wherein the transaction bit is changed from the first logical value to the second logical value, upon the first access to the cache line during pendancy of the transaction, and wherein the transaction bit is reset to the first logical value, upon commitment of the transaction.  
     
     
         30 . The system of  claim 27 , wherein execution by the execution unit is also re-vectored to a barrier associated with the cache line, if a cache-miss occurs.  
     
     
         31 . The system of  claim 27 , wherein the barrier includes a lock within an array of locks, the lock being indexed in the array of locks by at least a portion of an address referencing the cache line.  
     
     
         32 . The system of  claim 31 , wherein the lock represents an even number, if the lock is owned by a resource in the multi-resource processor, and an odd version number to represent a version of the cache line, if the lock is not owned by a resource in the multi-resource processor.  
     
     
         33 . A method comprising: executing a memory access instruction within a transaction, wherein the memory access instruction references a location in a shared memory; 
 accessing the location, without determining a state of a lock mapped to the location in the shared memory, if a transaction bit associated with the location represents a first value;    if the transaction bit associated with the location represents a second value, determining the state of the lock, 
 acquiring the lock and accessing the location, if the state of the lock represents an un-owned state,  
 setting the transaction bit to the first value; and  
   generating an eviction notification, if the location is evicted and the transaction bit associated with the location represents the first value.    
     
     
         34 . The method of  claim 33 , wherein the eviction notification is generated based on an eviction event selected from a group consisting of an eviction interrupt, an inspection of a eviction counter, and an eviction due to capacity constraints.  
     
     
         35 . The method of  claim 33 , wherein the state of the lock represents the un-owned state, if, the lock represents an odd integer version value, and the state of the lock represents an owned state, if the lock represents an even integer value.  
     
     
         36 . The method of  claim 35 , wherein acquiring the lock comprises writing the even integer value to the lock.  
     
     
         37 . The method of  claim 36 , further comprising: 
 if operating in an aggressive mode: 
 not storing the odd integer version value before writing the even integer value to the lock,  
 committing the transaction, if an eviction notification is not generated during a pendancy of the transaction, and  
 aborting the transaction, if an eviction notification is generated during the pendancy of the transaction.  
   
     
     
         38 . The method of  claim 37 , further comprising: 
 if operating in a cautious mode: 
 storing the odd integer version value before writing the even integer value to the lock,  
 committing the transaction, if an eviction notification is not generated during a pendancy of the transaction, and  
 validating the odd integer version value before committing the transaction, if an eviction notification is generated during the pendancy of the transaction.  
   
     
     
         39 . The method of  claim 38 , wherein the aggressive mode is a default mode, and wherein cautious mode operation occurs, if the transaction aborts a predetermined number of times.  
     
     
         40 . The method of  claim 33 , wherein accessing the location is selected from a group consisting of a read from the location, a write to the location, a load from the location, and a store to the location.  
     
     
         41 . A method comprising: 
 determining if an access referencing a location in a shared memory is a first access to the location during a pendancy of a transaction;    revectoring execution to a barrier associated with a location in the shared memory, if the access is the first access to the location during the pendancy of the transaction;    accessing the location in the shared memory, without revectoring execution to the barrier associated with the location in the shared memory, if the access is an access subsequent to the first access during the pendancy of the transaction.    
     
     
         42 . The method of  claim 41 , wherein the location is to store a plurality of elements, and wherein each of the plurality of elements is individually selected from a group consisting of an instruction, an operand, a data operand, and a grouping of logical values.  
     
     
         43 . The method of  claim 42 , wherein each element of the plurality of elements to be stored in the location is associated with a transaction bit, and wherein determining if the access referencing the location in the shared memory is a first access to the location comprises: 
 determining at least one element of the plurality of elements referenced by the access referencing the location;    checking the transaction bit associated with the at least one element of the plurality of elements;    determining the access referencing the location in the shared memory is the first access to the location, if the transaction bit associated with the at least one element represents a first value.    
     
     
         44 . The method of  claim 41 , wherein determining if the access referencing the location in the shared memory is a first access to the location comprises: 
 checking a transaction bit associated with the location;    determining the access referencing the location in the shared memory is a first access, if the transaction bit represents a first value.    
     
     
         45 . The method of  claim 44 , wherein re-vectoring execution to a barrier associated with the location in the shared memory, if the access is the first access to the location during the pendancy of the transaction comprises: 
 generating a transaction miss interrupt, if the transaction bit represents the first value;    executing a handler to handle the transaction miss interrupt, wherein handling the transaction miss interrupt includes checking the barrier associated with the location before accessing the location:    
     
     
         46 . The method of  claim 45 , wherein the barrier associated with the location includes a lock associated with the location in a hash table, wherein the lock is indexed in the hash table with a portion of an address referencing the location in the shared memory:  
     
     
         47 . The method of  claim 46 , further comprising: 
 accessing the location, after re-vectoring execution to the barrier and acquiring the lock associated with the location; and    setting the transaction bit associated with the location to represent a second value, after accessing the location:    
     
     
         48 . The method of  claim 47 , further comprising: 
 determining if the access is an access subsequent to the first access during pendancy of the transaction, wherein determining if the access is an access subsequent to the first access comprises: 
 checking the transaction bit associated with the location, and  
 determining the access is an access subsequent to the first access, if the transaction bit represents the second value.