System and Method for Executing Instructions Utilizing a Preferred Slot Alignment Mechanism

Abstract

A system and method for executing instructions utilizing a preferred slot alignment mechanism is presented. A processor architecture uses a vector register file, a shared data path, and instruction execution logic to process both single instruction multiple data (SIMD) instruction and scalar instructions. The processor architecture divides a vector into four “slots,” each including four bytes, and locates scalar data in “preferred slots” to ensure proper positioning. Instructions using the preferred slot mechanism include 1) shift and rotate instructions operating across an entire quad-word that specify a shift amount, 2) memory load and store instructions that require an address, and 3) branch instructions that use the preferred slot for branch conditions (conditional branches) and branch addresses (register-indirect branches). As a result, the processor architecture eliminates the requirement for separate issue slots, separate pipelines, and the control complexity for separate scalar units.

1 . A microprocessor comprising: 
 a shared data path that processes a vector register, wherein the vector register is selected from a plurality of vector registers included in a vector register file, and wherein each of the vector registers in the vector register file stores one of two types of data at a point in time, wherein the first type of data is parallel data and the second type of data is scalar data, the parallel data corresponding to data-parallel processing of an input program, and the scalar data corresponding to processing of a single data value of the input program; and    instruction execution logic coupled to the shared data path, the instruction execution logic processing the selected vector register in its entirety.    
   
   
       2 . The microprocessor of  claim 1  wherein the vector register file further comprises: 
 a plurality of read data access ports, wherein each of the plurality of read data access ports require reading from the selected vector register in its entirety in response to a read request; and    a plurality of write data access ports, wherein each of the plurality of write data access ports require writing to the selected vector register in its entirety in response to a write request.    
   
   
       3 . The microprocessor of  claim 2  wherein the instruction execution logic is adapted to: 
 execute a memory access instruction, wherein the memory access instruction performs reading address information from one of the plurality of read data access ports.    
   
   
       4 . The microprocessor of  claim 3  wherein the memory access instruction uses an address generated by adding a data address to a data address offset, the data address included in a preferred slot of the selected vector register, which is read using a first read data access port included in the plurality of read data access ports, and the data address offset included in a preferred slot of a second vector register included in the plurality of vector registers, which is read using a second read data access port included in the plurality of read data access ports.  
   
   
       5 . The microprocessor of  claim 2  wherein the instruction execution logic executes a data formatting instruction to insert at least one byte of data stored in the selected vector register into a second vector included in the plurality of vector registers, and wherein data formatting information corresponds to a relative position of at least one byte of information relative to a memory address of a vector that is stored in one of a local store and a memory, and wherein said first vector, second vector and the data formatting information are retrieved using the plurality of read data access ports.  
   
   
       6 . The microprocessor of  claim 2  further comprising: 
 branch execution logic that executes a branch to register instruction, wherein the branch execution logic retrieves a branch target address from a preferred slot of the selected vector register using one of the plurality of read data access ports.    
   
   
       7 . The microprocessor of  claim 2  further comprising: 
 branch execution logic that executes a conditional branch wherein a branch condition is retrieved by testing a condition stored in the preferred slot of the selected vector register using one of the plurality of read data access ports.    
   
   
       8 . The microprocessor of  claim 2  further comprising: 
 branch execution logic that executes a branch and link instruction wherein a link address is stored in the selected vector register using one of the plurality of write data access ports.    
   
   
       9 . The microprocessor of  claim 8  wherein the vector register file includes a plurality of slots, and wherein a write of link information includes: 
 an address in a first slot included in the plurality of slots; and    wherein the remaining plurality of slots include values that are selected from the group consisting of a zero value, a predefined value, and an undefined value.    
   
   
       10 . The microprocessor of  claim 9  wherein the microprocessor performs a code sequence that implements a function call return by executing a branch to register with a register specification corresponding to a specified register of a link instruction.  
   
   
       11 . The microprocessor of  claim 2  wherein a select instruction performs a bitwise select between two data values under control of a selection word stored in the selected vector register using one of the plurality of read ports.  
   
   
       12 . The microprocessor of  claim 1  wherein a rotate or shift instruction is performed under control of a count specified in a preferred slot, the count or shift being adapted to ignore high-order bits of the count.  
   
   
       13 . The microprocessor of  claim 12  wherein the rotate or shift instruction is used to implement a load and align sequence of a scalar word with a two instruction sequence comprising: 
 a first load instruction receiving an address to load an aligned vector word by ignoring a set of low order bits corresponding to a vector length; and    a second rotate or shift instruction receiving the address to align the scalar word by performing a rotate specified by the address, and ignoring high-order bits of the address that do not correspond to a vector length.    
   
   
       14 . The microprocessor of  claim 13  wherein data formatting information is used to extract data included in an entire vector register that is included in the plurality of vector registers.  
   
   
       15 . The microprocessor of  claim 1  wherein a data access instruction specifies an address in a local store operatively coupled to the microprocessor.  
   
   
       16 . The microprocessor of  claim 1  wherein the microprocessor executes an instruction to generate a data vector in the vector register file, wherein a first data word included in the data vector is used for additional computation, and at least one word in the data vector is not used for additional computation.  
   
   
       17 . The microprocessor of  claim 1  wherein a preferred slot is specified as a location to obtain a single data word from the selected vector register for instructions requiring a single data word input.  
   
   
       18 . The microprocessor of  claim 17  wherein the preferred slot is located at a leftmost word element slot included in each of the plurality of vector registers.  
   
   
       19 . The microprocessor of  claim 1  wherein each of the plurality of vector registers stores one of a plurality of data types at a point in time.  
   
   
       20 . A computer-implemented method comprising: 
 selecting a vector register from a plurality of vector registers included in a vector register file, wherein each of the vector registers in the vector register file stores one of two types of data at a point in time, wherein the first type of data is parallel data and the second type of data is scalar data, the parallel data corresponding to data-parallel processing of an input program, and the scalar data corresponding to processing of a single data value of the input program; and    processing the data included in the selected vector register in its entirety, wherein the processing includes obtaining the scalar data from a predefined range of bytes included in the selected vector register.