Selectable clock unit

Abstract

The present invention provides a memory device having a mode register with a selectable bit which sets the memory device to operate with a selected one of a plurality of possible clock input signals, for example, a single clock input or differential clock input.

1 - 32 . (canceled)  
   
   
       33 . A memory device comprising: 
 an input for receiving a clock signal having a specified frequency; and    a mode register having at least one programmable storage location for storing information identifying a type of clock input signal which will be used during operation of said memory device in one of a regular mode and a power saving mode.    
   
   
       34 . The memory device according to  claim 33  wherein said programmable storage location has a default setting for one type of clock input signal.  
   
   
       35 . The memory device according to  claim 34  wherein said one type of clock input signal is a single clock input signal.  
   
   
       36 . The memory device according to  claim 34  wherein said one type of clock input signal is a differential clock input signal.  
   
   
       37 . The memory device according to  claim 33  wherein said programmable storage location stores information indicating at least one of a first type of clock input signal and a second type of clock input signal.  
   
   
       38 . The memory device according to  claim 33  wherein in said power saving mode an amount of power used by said memory device is less than in said regular mode.  
   
   
       39 . A computing system comprising: 
 a processor; and    a memory device in communication with said processor, said memory device comprising a mode register having bits for setting operational parameters for said memory device, wherein at least one of said bits is capable of being set to identify a clock input signal which will be used during operation of said memory device in either a regular mode or a power saving mode.    
   
   
       40 . The computing system according to  claim 39  wherein in said power saving mode an amount of power used by said computing system is less than in said regular mode.  
   
   
       41 . The computing system according to  claim 39  wherein said clock input signal is a single clock input signal.  
   
   
       42 . The computing system according to  claim 39  wherein said clock input signal is a differential clock input signal.  
   
   
       43 . A control circuit for a memory device, comprising: 
 a mode register having at least one programmable storage location for storing information identifying a type of clock input signal which will be used during operation of a memory device in either a regular mode or a power saving mode; and    a logic circuit responsive to contents of said mode register for operating said memory device in either said regular mode or said power saving mode.    
   
   
       44 . The control circuit according to  claim 43  wherein said programmable storage location has a default setting for one type of clock input signal.  
   
   
       45 . The control circuit according to  claim 44  wherein said one type of clock input signal is a single clock input signal.  
   
   
       46 . The control circuit according to  claim 44  wherein said one type of clock input signal is a differential input signal.  
   
   
       47 . The control circuit according to  claim 43  wherein in said power saving mode an amount of power used by said control circuit is less than in said regular mode.  
   
   
       48 . The control circuit according to  claim 43  wherein said programmable storage location stores information indicating at least one of a first type of clock input signal and a second type of clock input signal.  
   
   
       49 . The control circuit according to  claim 48  wherein said first type of clock input signal is a single clock input signal and said second type of clock input signal is a differential clock input signal.  
   
   
       50 . The control circuit according to  claim 43 , wherein said memory device is capable of operating in response to more than one clock input signal.  
   
   
       51 . A method of operating a computing system comprising: 
 providing a clock signal generating device in communication with a memory device, wherein said memory device is programmed to operate in either a regular mode or a power saving mode according to a clock input signal from said clock signal generating device, and wherein said memory device has a mode register having a storage location for storing information identifying a type of clock input signal.    
   
   
       52 . The method according to  claim 51  wherein said clock input signal is a single clock input signal in said power saving mode.  
   
   
       53 . The method according to  claim 51  wherein said clock input signal is a differential clock input signal in said regular mode.  
   
   
       54 . A method for operating a memory system comprising: 
 providing a memory controller and a double data rate memory device having a mode register;    initializing said memory system to operate in a regular mode at a first clock input signal by sending a first signal from said memory controller to said mode register setting said double data rate memory device to operate at said first clock input signal and storing information identifying said first clock input signal in said mode register; and    changing said memory system to operate in a power saving mode at a second clock input signal by sending a second signal from said memory controller to said mode register to operate said double data rate memory device at said second clock input signal and storing information identifying said second clock input signal in said mode register, wherein said second clock input signal is different from said first clock input signal.    
   
   
       55 . The method according to  claim 54  wherein said first clock input signal is a differential clock input signal.  
   
   
       56 . The method according to  claim 54  wherein said second clock input signal is a single clock input signal.