Semiconductor device

Abstract

It is an object to provide a semiconductor device capable of holding multibit information in one memory cell also when scaling for a nonvolatile memory progresses, and a method of manufacturing the semiconductor device. A trench (TRI) is formed in a channel portion of an MONOS transistor. Then, a source side portion and a drain side portion in a silicon nitride film ( 122 ) of a gate insulating film ( 120 ) which interpose the trench (TR 1 ) are caused to function as first and second electric charge holding portions capable of holding electric charges (CH 1 ) and (CH 2 ). In the case in which the electric charges (CH 1 ) are trapped and the electric charges (CH 2 ) are then trapped, thus, a portion ( 130 a ) of a gate electrode ( 130 ) in the trench (TR 1 ) functions as a shield. If a fixed potential is given to the gate electrode ( 130 ), the second electric charge holding portion is not influenced by an electric field (EF 1 ) induced by the electric charges (CH 1 ) so that the trapping of the electric charges (CH 2 ) is not inhibited.

1 . A method of manufacturing a semiconductor device, comprising: 
 providing a semiconductor substrate having a trench formed in a surface of said semiconductor substrate; and    forming an MIS (Metal Insulator Semiconductor) transistor including the steps of 
 forming a source region formed to face said surface in said semiconductor substrate;  
 forming a drain region formed to face said surface in said semiconductor substrate, said drain region formed apart from said source region on an opposite side of said trench;  
 forming a gate insulating film formed on at least a portion of said surface which is interposed between said source region and said drain region within said trench; and  
 forming a gate electrode formed on said gate insulating film at least within said trench,  
   wherein the step of forming the gate insulating film includes forming first and second electric charge holding portions configured to hold an electric charge in said gate insulating film with said trench interposed therebetween.    
   
   
       2 . The method of  claim 1 , wherein the step of forming the gate insulating film includes forming a laminated film in which a first silicon oxide film, a silicon nitride film, and a second silicon oxide film are sequentially provided; and 
 said first and second electric charge holding portions are first and second portions in said silicon nitride film with said trench interposed therebetween, and are opposed to each other.    
   
   
       3 . The method of  claim 1 , wherein said first and second electric charge holding portions are not formed in a portion of said gate insulating film within said trench.  
   
   
       4 . Then method of  claim 1 , further comprising: 
 forming another MIS transistor having another source region, another drain region, another gate insulating film and another gate electrode on said semiconductor substrate.    
   
   
       5 . The method of  claim 4 , wherein said first and second electric charge holding portions are not formed in a portion of said gate insulating film which enters said trench and said another gate insulating film of said another MIS transistor is extended in said portion of said gate insulating film which enters said trench.  
   
   
       6 . The method of  claim 1 , wherein said first and second electric charge holding portions have ends on said source region and said drain region.  
   
   
       7 . The method of  claim 6 , further comprising forming insulating films for covering said ends of said first and second electric charge holding portions on said ends, respectively.  
   
   
       8 . The method of  claim 1 , wherein corner portions of an upper end and a bottom in said trench are rounded.  
   
   
       9 . The method of  claim 1 , wherein the step of forming the gate insulating film includes forming said first and second electric charge holding portions by a plurality of insular regions formed in said gate insulating film.  
   
   
       10 . The method of  claim 9 , wherein said insular regions are constituted by silicon or a silicon nitride film.  
   
   
       11 . The method of  claim 1 , wherein the step of forming the gate insulating film includes forming said first and second electric charge holding portions in said gate insulating film which is adjacent to a side surface of said trench.