Methods of Manufacturing Semiconductor devices Having Buried Bit Lines

Abstract

A semiconductor device includes a semiconductor substrate having a first conductivity type and having an upper portion, a pair of bit lines extending in a first direction and doped with an impurity of a second conductivity type opposite to the first conductivity type and spaced from one another in the upper portion of the semiconductor substrate, a first line formed between the pair of bit lines having a plurality of alternating recessed device isolation regions and channel regions, with each of the channel regions contacting each bit line of the at least one pair of bit lines, and word lines formed at right angles to the first lines and covering the channel regions.

1 . A method of forming a semiconductor device, comprising: 
 forming a plurality of bit lines spaced from one another and extending in a first direction in an upper portion of a semiconductor substrate having a first conductivity type, by selectively doping an upper portion of the substrate with an impurity of a second conductivity type that is opposite to first conductivity type;    forming a mask layer on a surface of the semiconductor substrate above the upper portion of the substrate;    forming a plurality of spaced apart recess regions extending through the mask layer and into the substrate between adjacent bit lines of the plurality of bit lines, each of the recess regions having a pair of opposing sidewalls oriented in parallel to a pair of adjacent bit lines and a pair of opposing sidewalls extending between a pair of adjacent bit lines;    depositing a first filling layer in the recess region;    removing the mask layer to expose the surface of the semiconductor substrate;    partially removing the first filling layer from the semiconductor substrate, to form a second filling layer exposing sidewalls of the recess regions;    forming an ONO layer on the surface of the semiconductor substrate including the sidewalls of the recess regions and the second filling layer; and    forming a gate electrode layer on the ONO layer over the sidewalls of the recess regions extending between adjacent pairs of bit lines.    
   
   
       2 . The method of  claim 1 , wherein the first conductivity type is P-type and the second conductivity type is N-type.  
   
   
       3 . The method of  claim 1 , wherein forming a plurality of spaced apart recess regions comprises defining a plurality of channel regions extending between adjacent pairs of bit lines.  
   
   
       4 . The method of  claim 3 , wherein the ONO layer covers the plurality of channel regions.  
   
   
       5 . The method of  claim 1 , wherein forming the recess region comprises: 
 forming a photoresist pattern for defining the recess regions on the mask layer; and    partially removing the mask layer and the semiconductor substrate in the shape of the photoresist pattern to form the recess region.    
   
   
       6 . The method of  claim 1 , wherein the first filling layer comprises an HDP oxide layer, TEOS, USG or a PECVD oxide.  
   
   
       7 . The method of  claim 1 , wherein a height of the sidewalls of the semiconductor substrate exposed by partially removing the first filling layer determines a width of the channel region.  
   
   
       8 . The method of  claim 1 , wherein forming the gate electrode layer comprises using the ONO layer as an etch stop layer.  
   
   
       9 . The method of  claim 1 , further comprising: 
 forming an insulating layer in the recess regions, the insulating layer extending above the bit lines adjacent to the recess regions; and    forming a bit line contact in the insulating layer for providing an external electrical connection to one of the plurality of bit lines.    
   
   
       10 . A method of forming a semiconductor device, comprising: 
 forming a plurality of bit lines spaced from one another and extending in a first direction in an upper portion of a semiconductor substrate of a first conductivity type by selectively doping portions of the upper portion of the substrate with an impurity of a second conductivity type that is opposite to first conductivity type;    forming a plurality of spaced apart recess regions extending between adjacent pairs of the plurality of bit lines and into the substrate, each of the recess regions having at least a pair of opposing sidewalls extending between a pair of adjacent bit lines;    partially filling the recess region with a filling layer;    forming an ONO layer on the surface of the semiconductor substrate including the filling layer and sidewalls of the recess regions; and    forming a gate electrode layer on the ONO layer over the opposing sidewalls of the recess regions.    
   
   
       11 . The method of  claim 10 , wherein the first conductivity type is P-type and the second conductivity type is N-type.  
   
   
       12 . The method of  claim 10 , wherein forming a plurality of spaced apart recess regions defines a plurality of channel regions extending between adjacent pairs of bit lines.  
   
   
       13 . The method of  claim 12 , wherein the ONO layer covers the plurality of channel regions.  
   
   
       14 . The method of  claim 10 , wherein the filling layer comprises an HDP oxide, TEOS, USG or a PECVD oxide.  
   
   
       15 . The method of  claim 10 , further comprising: 
 forming an insulating layer in the recess regions, the insulating layer extending above the bit lines adjacent to the recess regions; and    forming a bit line contact in the insulating layer for providing an external electrical connection to one of the plurality of bit lines.