Conditional negating booth multiplier

Abstract

An angle rotator performs angle rotation of an input complex signal in the complex plane according to an angle θ. The angle rotator includes a coarse stage rotation and a fine stage rotation. The two specific amounts of rotation are obtained directly from the original angle, without performing iterations as are performed by known CORDIC-type methods. The coarse stage rotation is performed using truncated approximations for the cosine θ M and the sine θ M , where θ M is a radian angle that corresponds to a most significant word (MSW) of the input angle θ. The fine stage rotation is performed using one or more error values that compensate for approximations and quantization errors associated with the coarse stage rotation. By partitioning the rotation into coarse and fine rotation stages, a two stage structure is obtained that requires much less hardware than a single-stage rotator, without sacrificing angle precision. This can occur because the two-stage rotator stores pre-computed cosine θ M and the sine θ M values in a small lookup table (e.g. memory device) for fast retrieval. Furthermore, the angle rotator consolidates all operations into a small number of reduced-size multipliers, enabling the use of efficient multiplier implementations, such as Booth encoding, thereby yielding a smaller and faster overall circuit. When higher precision is desired, more accurate results can be attained simply by increasing the wordlength and the multiplier size, without significantly increasing overall circuit latency.

1 . In a digital circuit, processing digital data, a circuit for selectively calculating a result value ±C equal to the product of a multiplicand A and an N-bit multiplier B represented by a plurality of multiplier bits b 0  . . . b N−1  or the negative of such product, respectively, comprising: 
 a selective negating circuit with a control input, where said selective negating circuit receives a plurality of said multiplier bits and outputs said plurality of multiplier bits in negated form in response to a first state of said control input and in non-inverted form in response to a second state of said control input;    a plurality of decoding circuits connected to the negating circuit, each decoding circuit receiving said plurality of multiplier bits and producing a partial product output by multiplying the multiplicand by a value based on a Booth algorithm decoding of said multiplier bits; and    summing means connected to said plurality of decoding circuits for summing said partial product outputs of said plurality of decoding circuits to produce a bit sequence representing the result value.    
   
   
       2 . The circuit of  claim 1 , where said control input comprises a negation control bit and said selective negating circuit comprises a circuit for calculating an exclusive-or of each of said multiplier bits with said negation control bit.  
   
   
       3 . In a digital circuit, processing digital data, a method of selectively calculating a result value ±C equal to the product of a multiplicand A and an N-bit multiplier B represented by a plurality of multiplier bits b 0  . . . b N−1  or the negative of such product, respectively, comprising the steps of: 
 (a) receiving a plurality of said multiplier bits and a control input;    (b) generating an output of said plurality of multiplier bits in inverted form in response to a first state of said control input and in non-inverted form in response to a second state of said control input;    (c) receiving said plurality of multiplier bits in a plurality of decoding circuits and producing a partial product output by multiplying the multiplicand by a value based on a Booth algorithm decoding of said multiplier bits; and    (d) summing said partial product outputs of said plurality of decoding circuits to produce a bit sequence representing the result value.    
   
   
       4 . The method of  claim 3 , wherein step (b) comprises the step of calculating an exclusive- or of each of said multiplier bits with at least one bit of said control input.