Memory system and memory card

Abstract

A memory system includes a plurality of nonvolatile memory chips (CHP 1 and CHP 2 ) each having a plurality of memory banks (BNK 1 and BNK 2 ) which can perform a memory operation independent of each other and a memory controller ( 5 ) which can control to access each of said nonvolatile memory chips. The memory controller can selectively instruct either a simultaneous writing operation or an interleave writing operation on a plurality of memory banks of the nonvolatile memory chips. Therefore, in the simultaneous writing operation, the writing operation which is much longer than the write setup time can be performed perfectly in parallel. In the interleave writing operation, the writing operation following the write setup can be performed so as to partially overlap the writing operation on another memory bank. As a result, the number of nonvolatile memory chips constructing the memory system of the high-speed writing operation can be made relatively small.

1 - 29 . (canceled)  
   
   
       30 . A nonvolatile memory apparatus comprising: 
 a first terminal used for inputting/outputting data;    a second terminal used for inputting an operation instruction command;    a third terminal used for inputting a clock instructing a timing of inputting/outputting data and inputting the operation instruction command;    a control unit which controls an operation according to the operation instruction command input from the second terminal; and    at least one nonvolatile memory used for storing data received via the first terminal based on control of the control unit,    wherein said nonvolatile memory has a plurality of memory cells, each of belonging to a corresponding one of a plurality of blocks, and is capable of performing a data storing operation for a first block during performance of a data storing operation for a second block.    
   
   
       31 . A nonvolatile memory apparatus according to  claim 30 , 
 wherein said nonvolatile memory has a plurality of signals for respective blocks, and    wherein each signal is for indicating whether the data storing operation is performing or not in an associated block.    
   
   
       32 . A nonvolatile memory apparatus according to  claim 31 , further comprising a second nonvolatile memory, 
 wherein the control unit issues a program command to a selected one of the nonvolatile memories, and is capable of issuing the program command to the other nonvolatile memory during performance of the data storing operation in the selected nonvolatile memory.    
   
   
       33 . A nonvolatile memory apparatus comprising: 
 a first terminal used for inputting/outputting data;    a second terminal used for inputting an operation instruction command;    a third terminal used for inputting a clock instructing a timing of inputting/outputting data and inputting the operation instruction command;    a control unit which controls an operation according to the operation instruction command input from the second terminal; and    at least one nonvolatile memory which performs a program operation for storing data received via the first terminal in accordance with a program command issued from the control unit,    wherein said nonvolatile memory has a plurality of memory cells, each belonging to a corresponding one of a plurality of blocks, and is capable of receiving the program command for storing data to a first block during performance the program operation for storing data to a second block.    
   
   
       34 . A nonvolatile memory apparatus according to  claim 33 , 
 wherein said nonvolatile memory has a plurality of signals for respective blocks, and    wherein each signal is for indicating whether the program operation is performing or not in an associated block.    
   
   
       35 . A nonvolatile memory apparatus according to  claim 34 , further comprising a second nonvolatile memory, 
 wherein the control unit operates to issue the program command to the second nonvolatile memory during performance the program operation in said one nonvolatile memory.    
   
   
       36 . A nonvolatile memory apparatus according to  claim 31 , 
 wherein the control unit operates to issue the program command to the second nonvolatile memory during performance the program operation in said one nonvolatile memory.