Contact formation

Abstract

The present disclosure includes various method, circuit, device, and system embodiments. One such method embodiment includes creating a trench in an insulator stack material having a portion of the trench positioned between two of a number of gates and depositing a spacer material to at least one side surface of the trench. This method also includes depositing a conductive material into the trench and depositing a cap material into the trench.

1 . A method of contact formation, comprising: 
 creating a trench in an insulator stack material having a portion of the trench positioned between two of a number of gates;    depositing a spacer material to at least one side surface of the trench;    depositing a conductive material into the trench; and    depositing a cap material into the trench.    
   
   
       2 . The method of  claim 1 , wherein the method includes depositing a liner material to the trench and spacer material.  
   
   
       3 . The method of  claim 1 , wherein the method includes creating a number of gates each having a cap that has a height of approximately 700 angstroms.  
   
   
       4 . The method of  claim 1 , wherein the method includes creating a number of gates each having a cap that has a height of 700 angstroms or less.  
   
   
       5 . The method of  claim 1 , wherein the method includes creating a number of gates each having a cap that has a height of 1500 angstroms or less.  
   
   
       6 . The method of  claim 1 , wherein the method includes depositing a silicon nitride layer over the number of gates prior to depositing an insulator stack material over the number of gates in which the first trench is to be created.  
   
   
       7 . The method of  claim 1 , wherein prior to creating a trench in the insulator stack material, creating an insulator stack layer formed from the insulator stack material and wherein the layer has a thickness between a top surface of the layer and a top surface of at least one gate of 1800 angstroms.  
   
   
       8 . The method of  claim 1 , wherein the method includes filling a number of open contacts with conductive material during the process of depositing the conductive material into the trench.  
   
   
       9 . The method of  claim 1 , wherein depositing a conductive material into the trench includes depositing a material selected from the group including: 
 Titanium;    Titanium Nitride;    Tungsten Nitride;    Tungsten; and    a combination of at least two of the above materials.    
   
   
       10 . A method, comprising: 
 applying an insulator material over a number of gates each having a gate cap to form an insulator stack;    creating a first contact opening between two of the number of gates;    filling the first contact opening with a filler material;    forming a trench having at least one side surface in the filler material;    coating the at least one side surface with a spacer material;    filling the trench with a conductive material;    forming a recess in the conductive material; and    filling the recess with a cap material.    
   
   
       11 . The method of  claim 10 , wherein the method includes applying a liner material to the trench and spacer material;  
   
   
       12 . The method of  claim 10 , wherein the method includes performing a dual masking technique to pattern a number of contacts in a contact array prior to filling the first contact opening with a filler material.  
   
   
       13 . The method of  claim 12 , wherein performing a dual masking technique to pattern a number of contacts includes patterning the number of contacts to a depth of at least 1500 angstroms.  
   
   
       14 . The method of  claim 13 , wherein performing a dual masking technique to pattern a number of contacts includes performing a contact dry etch technique to pattern the number of contacts.  
   
   
       15 . The method of  claim 10 , wherein forming the trench includes patterning the trench to a depth of approximately 1500 angstroms.  
   
   
       16 . The method of  claim 10 , wherein coating the at least one side surface with a spacer material includes applying a spacer dielectric to line the trench side wall.  
   
   
       17 . The method of  claim 10 , wherein coating the at least one side surface with a spacer material includes applying a material to a thickness of approximately 250 angstroms.  
   
   
       18 . The method of  claim 10 , wherein the method includes filling a number of periphery contact openings and interconnects with conductive material during the process of filling the trench with conductive material.  
   
   
       19 . A semiconductor structure, comprising: 
 a trench structure having at least one side wall formed in an insulator material;    a spacer material positioned on the at least one side wall;    a conductive material positioned within the trench structure; and    a cap material positioned over the conductive material.    
   
   
       20 . The semiconductor structure of  claim 19 , wherein the trench structure is a damascene trench structure.  
   
   
       21 . The semiconductor structure of  claim 19 , wherein the trench structure is formed along a path over a number of digit contacts and not over a number of cell contacts.  
   
   
       22 . The semiconductor structure of  claim 21 , wherein the trench structure is formed only over digit contacts.  
   
   
       23 . An integrated circuit, comprising: 
 a semiconductor substrate including a number of cell and digit contacts;    a trench structure positioned over the digit contacts, the trench structure having at least one side wall formed in an insulator material;    a spacer material positioned on the at least one side wall;    a conductive material positioned within the trench structure; and    a cap material positioned over the conductive material.    
   
   
       24 . The integrated circuit of  claim 23 , wherein the conductive material is positioned in a contact opening formed over a number of the digit contacts.  
   
   
       25 . The integrated circuit of  claim 24 , wherein the cap material is positioned in the contact openings for over the number of the digit contacts.  
   
   
       26 . A memory device, comprising: 
 a semiconductor substrate including a number of contacts;    a trench structure positioned over a number of the contacts, the trench structure having at least one side wall formed in an insulator material;    a spacer material positioned on the at least one side wall;    a conductive material positioned within the trench structure; and    a cap material positioned over the conductive material.    
   
   
       27 . The memory device of  claim 26 , wherein the cap material includes a dielectric material.  
   
   
       28 . The memory device of  claim 27 , wherein the cap material is a silicon nitride material.  
   
   
       29 . The memory device of  claim 26 , wherein the spacer material includes Tetraethyl Orthosilicate.  
   
   
       30 . The memory device of  claim 26 , wherein the filler material includes a sacrificial material.  
   
   
       31 . The memory device of  claim 26 , wherein the filler material includes a polysilicon material.  
   
   
       32 . An electronic system, comprising: a controller; and a memory device coupled to the controller, the memory device having an array of memory cells, the memory cells having: 
 a semiconductor substrate including a number of contacts;    a contact structure forming at least one of the contacts, the contact structure having at least one side wall formed in an insulator material;    a spacer material positioned on the at least one side wall;    a conductive material positioned within the contact structure; and    a cap material positioned over the conductive material.    
   
   
       33 . The electronic system of  claim 32 , wherein the memory is a dynamic random access memory device.  
   
   
       34 . The electronic system of  claim 32 , wherein the controller is a processor.