Formation of a disposable spacer to post dope a gate conductor

Abstract

A method of forming a doped gate structure on a semiconductor device and a semiconductor structure formed in that method are provided. The method comprises the steps of providing a semiconductor device including a gate dielectric layer, and forming a gate stack on said dielectric layer. This latter step, in turn, includes the steps of forming a first gate layer on the dielectric layer, and forming a second disposable layer on top of the first gate layer. A fat spacer is formed around the first gate layer and the second disposable layer. The second disposable layer is removed, and ions are implanted in the first gate layer to supply additional dopant into the gate above the gate dielectric layer, while the fat disposable spacer keeps the implanted ions away from the critical source and drain diffusion region.

1 - 12 . (canceled)  
   
   
       13 . A semiconductor structure, comprising: 
 a substrate including a gate dielectric layer;    a gate stack on the gate dielectric layer, said gate stack including a first gate layer on the dielectric layer and comprised of a first material, and a second layer on top of the first gate layer and comprised of a second material different than the first material; and    a disposable spacer extending around the gate stack, and extending upward above the substrate to a level higher than the top of the first gate layer.    
   
   
       14 . A semiconductor structure according to  claim 13 , wherein the disposable spacer thickness is equal or thicker than the first gate layer so that at least 2× fatter spacer is formed.  
   
   
       15 . A semiconductor structure according to  claim 13 , wherein the spacer extends upward substantially to the top of the gate stack.  
   
   
       16 . A semiconductor structure according to  claim 13 , further comprising a liner deposited on the gate stack between the gate stack and the spacer.  
   
   
       17 . A semiconductor structure according to  claim 16 , wherein said liner is also deposited on the semiconductor substrate, between said substrate and the spacer.