Dynamic random access memory

Abstract

DRAM includes a small capacitor as a storage device, a write MOS transistor as a write device, and a diode as a read device; the diode includes four terminals, the first terminal serves as a read word line, the second terminal serves as a storage node, the third terminal is floating, and the fourth terminal serves as a bit line; the diode can be composed of the parasitic bipolar transistor of the write MOS transistor with attaching one more terminal; the diode and the write MOS transistor can be formed from thin-film layer, thus multiple memory cells are stacked; the heavy routing lines are driven by the bipolar drivers which are part of the invention; the bipolar drivers and the control MOS transistors of the peripheral circuit can be formed from the thin-film transistor; hence the whole chip can be stacked over the wafer, such as silicon, quartz and others; additionally it applications are extended to a multi port memory and a content addressable memory.

1 . A memory device, comprising: 
 a memory cell, wherein a MOS transistor serves as a write device, a diode serves as a read device, and a capacitor stores data; and the MOS transistor includes a gate as a write word line, a source as a storage node, a drain as a bit line, and a body; and the diode includes four terminals, the first terminal serves as a read word line, the second terminal is connected to the storage node, the third terminal is floating, and the fourth terminal is connected to the bit line; and the capacitor is composed of an insulator between two electrodes, one electrode is connected to the storage node, and another electrode is connected to a plate line; and    a memory array, wherein main memory cells configure main columns, dummy memory cells configure dummy columns; and the first dummy column generates the first delay signal for enabling the main columns, after the read word line is enabled; and the far end dummy column generates the second delay signal to disable the read word line; and    a peripheral circuit including a row decoder which controls the read word line, the write word line and the plate line; and a read data latch wherein a latch node is connected to a current mirror, a feedback inverter and a pre-charge device; and the latch node is pre-charged by the pre-charge device during standby; when reading data “1”, the current mirror repeats the bit line current, thus the current mirror changes the latch node, after then, the bit line current is cut off by the output of the latch node, otherwise the latch node keeps the pre-charged voltage when reading data “0”; and an output driver receives the output of the latch node and transfers the received data to the output pad.    
   
   
       2 . The memory device of  claim 1 , wherein the four-terminal diode is composed of the parasitic bipolar transistor of the MOS transistor, the first terminal is added to the source of the MOS transistor which makes a p-n junction, the second terminal shares the source of the MOS transistor, the third terminal shares the floating body of the MOS transistor, and the fourth terminal shares the drain of the MOS transistor.  
   
   
       3 . The memory device of  claim 1 , wherein the diode includes four terminals, the first terminal is p-type, the second terminal is n-type, the third terminal is p-type, and the fourth terminal is n-type.  
   
   
       4 . The memory device of  claim 1 , wherein the diode includes four terminals, the first terminal is n-type, the second terminal is p-type, the third terminal is n-type, and the fourth terminal is p-type.  
   
   
       5 . The memory device of  claim 1 , wherein the diode is formed from silicon including polysilicon, amorphous silicon and stretchable silicon, germanium, compound semiconductor, and metal to form a Schottky diode.  
   
   
       6 . The memory device of  claim 1 , wherein the capacitor includes ordinary dielectric capacitor including high dielectric constant, and ferroelectric dielectric capacitor.  
   
   
       7 . The memory device of  claim 1 , wherein the capacitor includes a floating plate which configures a series capacitor.  
   
   
       8 . The memory device of  claim 1 , wherein the (local) bit line is connected to a (selected) global bit line through a transmission gate and the local bit line is located between the selected global bit line and the adjacent global bit line.  
   
   
       9 . The memory device of  claim 1 , wherein the current mirror of the read data latch includes lower threshold MOS transistor than that of control circuit in the chip.  
   
   
       10 . The memory device of  claim 1 , wherein the feedback inverter of the read data latch includes a current source which limits the current flow through the feedback inverter to have lower current than that of the current mirror when read data “1”, where the first dummy column sets up a current path which generates a bias voltage for regulating the current source of the feedback inverter.  
   
   
       11 . The memory device of  claim 1 , wherein the read word line driver includes the first bipolar transistor and the second bipolar transistor; and the first bipolar transistor provides the base current of the second bipolar transistor; and the second bipolar transistor drives the read word line.  
   
   
       12 . The memory device of  claim 1 , wherein the output driver includes the first bipolar transistor and the second bipolar transistor; and the first bipolar transistor provides the base current of the second bipolar transistor; and the second bipolar transistor drives the pull-up portion of the output node; and the third bipolar transistor and the fourth bipolar transistor; and the third bipolar transistor provides the base current of the fourth bipolar transistor; and the fourth bipolar transistor drives the pull-down portion of the output node.  
   
   
       13 . The memory device of  claim 1 , wherein at least one terminal of the diode is vertically formed on the other terminal of the diode.  
   
   
       14 . The memory device of  claim 1 , wherein the memory cells are formed in between the routing layers.  
   
   
       15 . The memory device of  claim 1 , wherein the memory cells are formed on the peripheral circuit.  
   
   
       16 . The memory device of  claim 1 , wherein multiple memory cells are stacked.  
   
   
       17 . The memory device of  claim 1 , wherein the peripheral circuit is formed on the silicon substrate, such as the conventional bulk wafer, the compound semiconductor wafer or the SOI (Silicon-on-Insulator) wafer.  
   
   
       18 . The memory device of  claim 1 , wherein the peripheral circuit is formed on the substrate, such as, a quartz wafer, a ceramic wafer, a glass, or a metal.  
   
   
       19 . The memory device of  claim 1 , wherein the capacitor is shared by multiple access devices including the read diode and the write MOS transistor, in order to configure multi port memory.  
   
   
       20 . The memory device of  claim 1 , wherein the peripheral circuit includes at least one compare circuit to configure a content addressable memory as an additional component; and the compare circuit includes the first transistor set and the second transistor set, wherein the first signal set couples to control a conduction state of the first transistor set and the second signal set couples to control a conduction state of the second transistor set, wherein the first signal set includes stored data in the memory cell and the second signal set includes comparand data from an input device; and at least one compare circuit coupled among the memory cells and at least one match line to receive first and second signal sets and affect a logical state of the match line in response to a predetermined logical relationship between the first and second signal sets.