Data transfer control method, and peripheral circuit, data processor and data processing system for the method

Abstract

A memory 1 performs its internal operation in response to access requests ( 200, 201 and 202 ) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 incorporated therein and according to said access requests, and outputs a response request 103 for said access requests to said CPU in synchronism with its internal operation. The CPU performs the access requests for the memory, and fetches data from the outside or outputs the data to the outside in response to and in synchronism with the response request 103 from the accessed memory and according to the kinds of said access requests.

1 .- 13 . (canceled)  
   
   
       14 . A semiconductor circuit device for control semiconductor memory devices arranged for external of the semiconductor circuit device, comprising: 
 a clock terminal which receives an clock signal to be operated the semiconductor circuit device synchronously;    address terminals which outputs a plurality of address signals to the semiconductor memory device;    data terminals which receives data signals from the semiconductor memory device;    control terminals which outputs control signals which requests to outputting the data signals of the semiconductor memory device; and    timing terminal which receives timing signals from the semiconductor memory devices;    wherein the clock terminal, the address terminals, the data terminals, the control terminals and the timing terminal are coupled to the semiconductor memory devices,    wherein the timing signal is asynchronously from the clock signals, and    wherein the data signals are latched in synchronism with the timing signal.    
   
   
       15 . A semiconductor circuit device according to  claim 14 , 
 wherein the semiconductor memory devices are random access memory or read only memory.    
   
   
       16 . A semiconductor circuit device according to  claim 15 , 
 wherein the semiconductor memory devices are random access memory devices which has a continuous data output function.    
   
   
       17 . A semiconductor circuit device according to  claim 14 , 
 wherein the semiconductor circuit device outputs data signals to be received the semiconductor memory devices in synchronism with the timing signal from the semiconductor memory devices.    
   
   
       18 . A semiconductor circuit device according to  claim 14 , 
 wherein the control signal are outputted in synchronism with the clock signal.